PCB Edge Quality Inspection: V-Cut, Routed Edge and Burr Acceptance Criteria

Most quality arguments between a buyer and a PCB supplier are about something measurable. Impedance

missed the window. A hole came in undersized. Solder mask registration slipped. Those fights are

short, because both sides can point at a number in a spec.

Board edge disputes are different. A batch arrives, someone in receiving inspection runs a finger

along a routed edge and finds a burr. Someone else finds a V-cut score that broke unevenly and left

a ragged nub of laminate on one side. Someone flags a corner where the edge looks slightly opened up.

Then the argument starts, and it goes nowhere, because nobody wrote down what a good edge looks like.

The supplier says the boards passed. The buyer says they are not usable. Both are being honest. The

purchase order simply never contained a sentence that either side could inspect against.

This is a sourcing and contract problem more than a manufacturing one. The fix is to decide, before

the PO goes out, which edge characteristics are inspectable pass/fail items, which ones only exist as

a mutually agreed number, and which ones are consequences of your own panel design that no supplier

can inspect away. This guide sorts the four common edge defect families into those buckets and shows

what each one needs to look like in your PO and in your first-article report.

Why board edge defects surface at receiving, not before

Three structural reasons, and all three are worth understanding before you write any criteria.

Depaneling is nearly the last thing that happens. By the time a panel is scored or routed into

individual boards, it has already passed electrical test and optical inspection. The edge is created

after most of the inspection gates are behind it. Whatever the depaneling step does to the board is,

in process terms, very close to the end of the line.

Edge quality is partly designed in, not just built in. Score line placement, the gap between

board outlines in the array, tab and mouse-bite layout, whether copper or plated features sit close

to the board outline, whether the array is scored in one direction or two — those come from the panel

drawing, which usually originates with the buyer or the buyer's design house. A supplier working to a

panel drawing that puts copper right at the edge cannot inspect its way out of the consequences.

There is no single universal number. For most edge characteristics, the standards give you

categories, defect definitions and class-based judgement language rather than one dimension that

applies to every board. IPC-A-600 addresses edge and laminate conditions with acceptance language

tied to product class, and IPC-6012 sets qualification and performance requirements by class. Neither

one hands you a residual thickness figure for your specific board thickness and score geometry.

That figure is something you and your supplier agree on. If you never agree on it, you have no

criterion, and receiving inspection becomes an opinion contest.

Put those three together and the pattern is clear: edge quality is the characteristic most likely to

be defined nowhere, created late, and inspected first by the person paying for it.

The four defect families, and who actually owns each one

Sorting by ownership matters more than sorting by appearance, because ownership tells you where the

sentence has to go — into the PO, into the panel drawing, into the first-article report, or into an

engineering conversation before you buy anything.

1. V-cut residual thickness and break quality — agreed number, not a standard number

V-scoring cuts a groove from both faces and leaves a web of material holding the array together

until someone snaps it. The remaining web is the residual thickness, sometimes called remaining web

or remaining thickness.

Too much residual and the board fights you when you break it, which stresses the laminate and

anything mounted near the score line. Too little and the array sags, boards separate in transit, or

they break during assembly handling before you wanted them to.

The correct residual depends on your board thickness, your material, your array size, how much mass

sits on the panel during assembly, and whether you break by hand or in a fixture. There is no

industry constant to cite. This is a number you request, the supplier confirms against their scoring

capability, and both sides then write into the drawing. Ask for it as a nominal value with a

tolerance band, not as a maximum, because a one-sided limit lets the actual value drift toward the

other side of what you needed.

Owner: shared, and it must be frozen in writing before production.

2. Routed edge burrs, nicks and roughness — inspectable, if you define the method

Milled or routed edges come off a rotating cutter. The realistic outcomes are some degree of surface

roughness, resin smear, small nicks, and burrs — particularly where copper crosses or approaches the

routed path, since copper deforms rather than fracturing cleanly.

This family is genuinely inspectable. But an inspectable criterion needs three parts, and buyers

routinely supply only the first:

• What the limit is (a dimensional limit, or a visual standard, or a defined class)
• How it is measured or judged (magnification, tactile check, comparison to a boundary sample)
• Where on the board it applies (whole perimeter, or specific edges such as a card-edge insertion

area or a connector datum edge)

"No burrs" fails all three at once. It is not achievable as an absolute, it has no method, and it

does not distinguish an edge that slides into a card guide from an edge nobody ever touches.

Owner: supplier, once you have supplied a limit and a method.

3. Edge delamination, haloing and laminate separation — standards-governed defect

Whitish areas along a cut edge, separation between layers, or a halo spreading inward from the edge

are laminate integrity conditions. Unlike residual thickness, this family is a recognised defect

type with acceptance language in IPC-A-600 that varies by product class.

This means two things for your PO. First, you must state a class. Class 2 and Class 3 do not accept

the same conditions, and a PO with no class stated invites the supplier to work to the lower one.

Second, once class is stated, this one is largely on the supplier — with the standing exception that

a panel design forcing an aggressive cut close to internal features increases the risk, which is why

it belongs in a pre-production engineering review rather than in a receiving argument.

Owner: supplier, against a class you must name.

4. Plated, exposed or copper-bearing edges — design-defined, must be called out

Plated half-holes along a board edge, castellations, deliberately plated edges for shielding or

grounding, or exposed copper at the outline are all cases where the edge itself is a functional

feature. The depaneling method interacts directly with them: a scoring line through a castellated

edge behaves very differently from a routed pass, and burr behaviour at plated features is not the

same as at bare laminate.

If your board has any of these and the RFQ does not say so, you have not really quoted the board you

designed. Two suppliers will assume two different depaneling approaches and two different edge

outcomes, and their prices will not be comparable either.

Owner: buyer, at RFQ time. This one is on you to declare.

There is a fifth item worth naming, though it is not a defect family: **dimensional tolerance of the

routed outline** — how closely the finished board matches your outline dimensions. Buyers often

merge this with edge quality, but it is a separate characteristic with a separate tolerance, and it

should be stated separately in the drawing.

The three V-cut parameters that must exist on paper

Of the four families, V-cut causes the most receiving-inspection disputes per dollar of board value,

because it is the one where buyers most often assume a default exists. It does not. Three parameters

need to be written down, and none of them has an industry default you can lean on.

Residual thickness, as nominal plus tolerance. State the target web thickness you want left after

scoring, with a band. Derive the target from how the array will be handled: a panel that goes through

reflow with heavy components, or that a machine breaks in a fixture, wants a different value than a

small light array snapped by hand. Ask the supplier to confirm the value is inside their scoring

capability for your board thickness and material before it becomes a PO line.

Score line position and which edges are scored. Which board outlines are scored, which are

routed, and whether the array is scored in one axis or both. Mixed arrays — scored on two sides and

routed on the other two — are common and completely fine, but they must be drawn, not implied.

Keep-out from the score line. How far copper, components and any plated feature must stay back

from the score. This is a design rule you own. If you place copper into the score path, you have

guaranteed a burr and a possible short, and no acceptance criterion will save you. Confirm the

keep-out with the supplier's engineering team for your specific stackup and score geometry rather

than reusing a number from an unrelated project.

A fourth item is worth adding when it applies: the break method you intend to use. If assembly will

break the array in a fixture rather than by hand, say so. It changes what residual thickness is

appropriate and it changes what "acceptable break edge" means.

How to make routed edges and burrs inspectable

Routed edges are the family where you can get to a real pass/fail gate, provided you write all three

components of a criterion. A workable clause looks like this in structure:

• Applicability: which edges. Name the perimeter, and separately name any edge with a function —

a card-edge contact area, an edge that registers against a fixture, an edge that slides into a

guide or an enclosure slot.

• Judgement basis: state the standard and class you are buying to (for example IPC-A-600 at your

named class), plus any additional dimensional limit you require on the functional edges.

• Method: inspection magnification or the visual condition under which the judgement is made,

and whether a tactile check is part of it. If you care about burrs you can feel rather than burrs

you can see, say that, because the two are different tests.

• Boundary samples: for anything cosmetic, agree a physical accept/reject sample pair during

first article. This resolves more future arguments than any amount of clause drafting, because it

converts a judgement into a comparison.

One practical note on the functional edges: if an edge has a job, give it its own line in the drawing

rather than folding it into a general perimeter statement. Suppliers optimise against what is called

out. An edge described only by a blanket perimeter note will be treated like every other edge.

What the first-article and lot inspection reports should contain

The report is where your criteria either become real or quietly disappear. Ask for these on the first

article, and specify which of them repeat on every lot.

On the first article:

• Measured V-cut residual thickness, as actual readings against your nominal and tolerance, taken at

more than one location on the array

• Confirmation of score and rout assignment matching the panel drawing
• Edge condition assessment against the named standard and class, with the class stated on the report

rather than assumed

• Photographs of a representative routed edge and a representative broken score edge
• Agreed boundary samples identified and retained, if you are using them
• Measured finished outline dimensions against the drawing tolerance
• For plated or castellated edges: explicit confirmation of how they were depaneled

On every lot, at minimum:

• Edge condition against the named standard and class, sampled per your agreed sampling plan
• V-cut residual thickness, at least as a sampled measurement, if V-cut is used
• Outline dimensions per the sampling plan

The point of naming this list in the PO is not paperwork volume. It is that a supplier who has to

report a number will control that number. A characteristic that appears on no report is a

characteristic nobody is controlling, and it will drift until it reaches the person opening the box.

A PO attachment you can adapt

A short attachment beats a long clause. The structure below covers the four families and stays

inside things both sides can actually check. Fill the bracketed items with values your engineering

contact has confirmed for your board.

```

BOARD EDGE AND DEPANELING REQUIREMENTS (attachment to PO [___])

1. Standard and class

All edge and laminate edge conditions to IPC-A-600, Class [2 or 3].

Board to be manufactured and qualified to IPC-6012, Class [2 or 3].

1. Depaneling method

Method per panel drawing rev [___]: scored edges [___], routed edges [___].

No substitution of depaneling method without written approval.

1. V-cut (if used)

Residual web thickness: [___] nominal, tolerance [+/- ___].

Measured and reported on first article at [___] locations per array.

Score-to-copper keep-out per panel drawing; supplier to flag any violation

before production rather than at shipment.

Intended break method: [by hand / in fixture].

1. Routed edges

Perimeter edge condition: per clause 1.

Functional edges [list them]: additional requirement [___],

judged at [___] magnification, tactile check [required / not required].

Boundary accept/reject samples to be agreed at first article: [yes / no].

1. Plated, castellated or copper-bearing edges

Present: [yes / no]. If yes, features and locations: [___].

Depaneling approach for these features to be confirmed in writing before production.

1. Outline dimensions

Finished outline tolerance: [___] per drawing rev [___].

1. Reporting

First article report to include items listed in [___].

Lot reports to include edge condition, V-cut residual (if applicable),

and outline dimensions per sampling plan [___].

1. Change control

Any change to depaneling method, score geometry or array layout requires

written buyer approval and a new first article.

```

Two things to notice about that template. Every technical value is a bracket, not a number — the

values belong to your board and must come from an engineering confirmation, not from a template.

And clause 8 is doing more work than it looks like: a change in array layout or depaneling method

between the sample you approved and the production lot you received is a frequent root cause of

"the first batch was fine and the second was not."

Where this sits in a sourcing conversation

Edge and depaneling requirements are cheap to specify at RFQ and expensive to negotiate after

delivery. Practically, that means raising them at three moments.

At RFQ, declare plated or functional edges and state your class. At panel drawing review, settle

score-versus-rout assignment, keep-outs and residual thickness with the supplier's engineering side.

At first article, capture the measurements and agree boundary samples. After that, change control

carries it.

If you are preparing an RFQ now and are unsure which of these apply to your board, send the panel

drawing and outline for engineering review before you set the acceptance numbers. Our

capabilities overview covers the process scope, and the

quote request route is the fastest way to get the depaneling questions answered against

your actual array rather than against a generic template. For related inspection topics, see our

PCB quality inspection methods guide, and for boards

where edge features interact with layer count and construction, the

multilayer PCB stackup guide and the

multilayer PCB product page give useful background. Assembly-side

handling of scored arrays is covered under PCB assembly.

FAQ

Is there a standard V-cut residual thickness I can just specify?

No. Residual thickness depends on board thickness, material, array size, component mass during

assembly and how the array will be broken. It is an agreed value between you and your supplier, and

it should be confirmed against their scoring capability for your specific board before it goes into

a PO or drawing.

Can I require zero burrs on routed edges?

Not usefully. Routing creates some edge condition by nature, so an absolute has no method and no

achievable target. Specify a class from the applicable standard, add a dimensional or tactile limit

on the edges that have a function, and agree boundary samples for cosmetic judgement.

Whose fault is a burr at a plated edge feature?

It depends on whether the RFQ disclosed the feature. Plated half-holes, castellations and copper at

the outline change how depaneling behaves. If the feature was declared and the depaneling approach

agreed, edge condition is the supplier's to control. If it was never declared, the buyer has quoted

a different board than the one designed.

Does edge delamination automatically mean the lot is rejectable?

It depends on the condition and the class you bought to. Edge and laminate conditions are addressed

in IPC-A-600 with acceptance language that differs by product class, which is why a PO with no class

stated is so weak. Name the class and the question becomes answerable.

What is the single highest-value thing to add to an existing PO?

A stated standard and class, plus a first-article report requirement covering V-cut residual and

edge condition. Those two additions convert most edge arguments from opinion into a measurement

against a document.

Should outline dimensional tolerance be part of the edge clause?

Keep it separate. How closely the finished board matches your outline is a different characteristic

from what the cut edge looks like, and merging them tends to leave one of the two undefined. Give

each its own line in the drawing.

We approved a first article and the second lot looked worse. What went wrong?

Most often a change in array layout, score geometry or depaneling method between the two. This is

why written change control tied to a new first article belongs in the PO — without it, a process

change that is invisible to you is also uncontested.

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