Complete PCB Via Design Guide: Through-Hole, Blind, Buried, and Microvias

Introduction
In multilayer PCB design, vias are the only pathway for electrical interconnection between layers. As electronics trend toward higher density, faster speeds, and smaller form factors, via design has evolved from simply "drilling a hole" into a systematic engineering discipline that must balance electrical performance, signal integrity, manufacturability, and cost.
An improperly designed via can cause impedance discontinuities, signal reflections, increased crosstalk, or reduced manufacturing yield. This guide systematically introduces the characteristics, design rules, and process requirements of each via type.
Via Types Overview
Four Major Via Types Compared
| Type | Structure | Typical Diameter | Aspect Ratio | Process Complexity | Cost |
|---|---|---|---|---|---|
| Through-Hole (PTH) | Penetrates all layers | 0.2-0.5mm | ≤10:1 | Low | 1× |
| Blind Via | Outer layer to inner layer | 0.1-0.3mm | ≤1:1 | Medium | 2-3× |
| Buried Via | Between inner layers only | 0.1-0.3mm | ≤1:1 | High | 3-5× |
| Microvia | Single or dual layer connection | 0.05-0.15mm | ≤0.8:1 | High | 3-4× |
Through-Hole Vias (PTH)
The most traditional and widely used via type, penetrating all PCB layers.
Standard Design Rules:
- Finished hole diameter: 0.2mm (minimum) to 0.5mm (standard)
- Pad diameter: hole diameter + 0.2mm (minimum annular ring 0.1mm)
- Aspect ratio: ≤ 10:1 (standard), ≤ 12:1 (advanced)
- Barrel copper thickness: ≥ 20μm (IPC Class 2), ≥ 25μm (IPC Class 3)
Parasitic Parameters:
| Parameter | Typical Value | Impact |
|---|---|---|
| Parasitic inductance | 0.5-1.5nH | Increased HF impedance |
| Parasitic capacitance | 0.3-0.8pF | Signal bandwidth limitation |
| Equivalent impedance | 40-70Ω | Impedance discontinuity |
Stub Effect and Back-Drilling
At speeds above 5Gbps, the unused via stub creates resonance at specific frequencies. Back-drilling removes the unused stub portion using a larger drill bit from the opposite side.
Back-drilling results:
| Metric | Before | After | Improvement |
|---|---|---|---|
| Insertion loss @10GHz | -3.5dB | -1.2dB | 66% |
| Return loss @10GHz | -8dB | -18dB | 10dB |
| Eye opening | 65% | 85% | 20% |
| Usable bandwidth | 8GHz | 20GHz+ | 2.5× |
Blind and Buried Vias
Blind vias connect an outer layer to one or more inner layers without penetrating the full board. Buried vias exist entirely within the PCB interior.
Key advantages:
- Save routing space on non-connected layers
- Naturally eliminate stub problems
- Enable higher routing density for fine-pitch BGAs
- Reduce parasitic parameters
Manufacturing considerations:
- Blind vias require controlled-depth drilling or laser ablation
- Buried vias require sequential lamination (sub-board fabrication first)
- Both increase cost significantly over standard through-holes
Microvias and HDI Technology
HDI Levels
| HDI Level | Structure | Laser Drill Passes | Typical Application |
|---|---|---|---|
| 1+N+1 | Single lamination blind via | 1 | Smartphones, tablets |
| 2+N+2 | Double lamination blind via | 2 | High-end phones, AP |
| 3+N+3 | Triple lamination blind via | 3 | Flagship phone SoC |
| Any Layer | Any-layer interconnect | Multiple | Highest-end applications |
Stacked vs. Staggered Microvias
Stacked vias align vertically across multiple layers for minimum footprint but require via-fill plating for reliability. Staggered vias offset between layers, offering easier manufacturing at slightly larger area cost.
Via Fill Plating
Via filling is essential for:
- Stacked via reliability
- Via-in-Pad BGA assembly
- Thermal conductivity
- Impedance predictability
| Process | Fill Material | Flatness | Conductivity | Cost |
|---|---|---|---|---|
| Resin plug | Epoxy resin | ±15μm | None | Low |
| Resin plug + cap plate | Resin + copper | ±5μm | Surface only | Medium |
| Copper fill plating | Pure copper | ±3μm | Full | High |
| Conductive paste | Silver/copper paste | ±10μm | Partial | Medium |
High-Speed Via Optimization
For differential signals (PCIe, USB, Ethernet):
- Maintain symmetry between differential pair vias
- Match via spacing to trace spacing
- Add ground vias adjacent to signal vias for return path
- Optimize anti-pad sizes on non-connected layers
- Consider non-circular anti-pads for precise impedance control
Conclusion
Via design bridges electrical performance, signal integrity, and manufacturability in PCB design. The right via type depends on signal speed, routing density, reliability class, and cost budget.
PCB168 offers full-range via processing capabilities from standard through-holes to advanced HDI (Any Layer), supporting minimum 0.075mm laser microvias, copper-fill plating, and precision back-drilling (±0.05mm). Whether for high-density consumer electronics HDI boards or high-speed communication backplanes, we deliver reliable manufacturing solutions.
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