12 or 16 Layer HDI PCB: How Layer Count Sets Your Lamination Cycles

A layer count feels like the most solid number in an HDI RFQ. It is an integer, it comes straight off the stackup, and nobody argues about what "16" means. So it gets written down first and then treated as settled.

It is not settled. On HDI, layer count on its own does not describe a buildable object. The same 16 layer HDI PCB can be two different products, with two different process routes, two different risk profiles and two genuinely incomparable quotes — depending on one other field that buyers routinely leave blank.

That field is the buildup form. PCB168 publishes it on the HDI PCB page as a range: 1+N+1 through 4+N+4. This article is about what that notation actually commits you to, how it converts a layer count into a lamination sequence, and how to write both fields so the quotes you get back are describing the same board.

What the m+N+m notation is actually counting

The m+N+m form is a standard way of describing a sequentially built board, and the convention follows the general buildup naming used in IPC-2226. Read it left to right as: outer HDI layers, core, outer HDI layers.

• N is the conventionally laminated core in the middle. It is built the way a normal multilayer board is built, and it can be drilled through mechanically.
• m is the number of HDI layers added to each side of that core, one at a time.

So 1+N+1 means one microvia layer added to each face of the core. 4+N+4 means four added to each face. The total layer count is 2m + N.

Here is the part that matters commercially: m is not a description, it is a count of build stages. Each of those m layers is added in its own press cycle, with its own laser drilling, plating and imaging steps in between. The core itself was laminated before any of that started.

That gives you a direct relationship you can reason about without needing any supplier-specific number:

> The number of lamination stages is driven by m, not by total layer count. The core contributes its own lamination. Each HDI tier adds another.

This is why the notation exists at all. If layer count were sufficient, nobody would have needed a second field.

One layer count, two different purchases

Work the arithmetic with total layer count held constant at 16 and you can see the problem immediately.

All four rows are 16 layers. All four are legitimate reads of "16 layer HDI." The last three are materially different manufacturing objects.

Consider what changes as you move down that table with the layer count unchanged:

Process stages multiply. Higher m means more press cycles, and each cycle brings its own laser drilling and plating passes. Material already pressed gets pressed again. Nothing about that is captured by the number 16.

Registration gets harder to hold. PCB168 publishes layer-to-layer registration at ±25μm on the HDI page. That figure is the outcome of dimensional behaviour across the whole sequence, not a fixed machine setting. A 4+N+4 build has to hold it across more accumulated stages than a 1+N+1 build does.

Via structure decisions appear. With m=1 there is only one microvia tier per side, so there is nothing to stack or stagger. From m=2 upward, how tiers connect becomes a real declaration you have to make — which is a separate field with its own consequences, and is not something layer count implies.

Risk concentration shifts. In a 1+N+1 build most of the layer count lives in a conventionally laminated core. In a 4+N+4 build much more of it lives in sequentially added tiers. Same 16 layers; different distribution of where things can go wrong.

None of this requires anyone to quote you a press-cycle number. The point is structural: m sets the sequence, and if m is blank, the sequence is whatever the supplier assumed.

What "16 layer HDI" gets interpreted as

Leave the buildup field empty and each supplier fills it in privately. Three things then happen, and all three cost you.

The quotes stop being comparable. Supplier A assumes 1+N+1 and returns a low number. Supplier B assumes 2+N+2 and returns a higher one. You read that as a price spread. It is not — it is two different boards. The cheapest quote may simply belong to the supplier who assumed the least.

The assumption surfaces after you commit. A buildup assumption does not stay hidden. It reappears at engineering review, or at the first article, as a requote or a schedule change. You have not avoided the decision, only deferred it to the worst moment to make it.

You lose the ability to ask why. If you declare 2+N+2 and a supplier proposes 1+N+1 instead, that is a useful conversation about whether your density really requires two tiers. If you declared nothing, there is no proposal to interrogate, because there was no baseline to deviate from.

The related failure is treating a higher m as a better spec. It is not. Higher m adds sequential stages, and stages accumulate risk. The right buildup is the lowest m your routing density actually needs — which is a question about whether your escape routing and via structure fit in fewer tiers, not a question about which number looks more capable.

If you have not yet established that HDI is the right construction at all, that question comes first: HDI or conventional multilayer, as an RFQ decision covers it, and this article assumes you are already past it.

Outside the 4–20 band: two published figures, do not merge them

When your layer count falls outside the range published for the HDI board type, a specific wording problem appears, and it is easy to get wrong.

PCB168 publishes two layer-count figures on two different pages:

• HDI PCB page: 4–20 layers, for that board type.
• Capabilities page: 1–40 layers, as a general fabrication range.

These are not interchangeable, because their scopes differ. A count of 21 to 40 sits inside the general range and outside the HDI board type's published band. That is not a case where you can assume the wider figure automatically applies to an HDI construction, because HDI construction carries sequential lamination with it and a general layer-count range does not imply it.

Do not swing to the other extreme and conclude it cannot be done either. The correct handling is to write it as an explicit open item:

> 28 layers, HDI construction required. Noting 4–20 layers published on the HDI PCB page and 1–40 layers published on the capabilities page. Please confirm whether this layer count is achievable as an HDI construction, and state the feasible buildup form in the written quotation.

That paragraph does three things: it gives the number, it names which published figure you are citing, and it demands the answer in writing. It does not declare any capability on the supplier's behalf.

An equally legitimate path is to question the construction itself. A layer count above the band often indicates that conventional multilayer with localised HDI would suit better, or that the density belongs on the IC substrate side. Raising that question is more likely to get you a buildable answer than forcing a layer count through. How conventional multilayer stacks are organised is covered in the multilayer PCB stackup guide, useful here as a comparison point.

What to write, and at what depth

Three depths, same logic as any other RFQ field: declare as much as you can defend, and mark the rest as open rather than leaving it silent.

Depth 1 — layer count only, buildup explicitly open.

> 16 layers, HDI. Buildup form not yet fixed — please propose within your published 1+N+1 to 4+N+4 range and state the form you quoted.

Weak on constraint, but honest, and it does the one thing that matters: it forces the assumption into the reply. Use it when routing is not finished. This is not the same as writing "16 layer HDI" and stopping — the difference is that you have made the open item visible and requested it back in writing.

Depth 2 — layer count plus buildup form.

> 16 layers total, 2+N+2 buildup, N=12 conventionally laminated core.

This is the depth most RFQs should reach. You have declared the sequence, so every quote prices the same object. Spell out N explicitly: 2+N+2 with 16 total layers implies N=12, but writing it removes the arithmetic from the supplier's side of the conversation.

Depth 3 — layer count, buildup, and tier-by-tier detail.

Depth 2 plus which layer pairs each tier connects, and how tiers relate to each other. Appropriate when you are transferring a qualified build, or when your via structure is genuinely fixed by package escape requirements. Understand the trade: you have removed the supplier's ability to propose a route that suits its qualified process, and you now own the structure entirely. Depth 3 is a deliberate cost you accept for control, not a free upgrade in rigour.

The material declaration sits alongside all three of these and interacts with them directly — sequential lamination is exactly where material behaviour stops being a datasheet question and becomes a yield question, because each press cycle reapplies heat and pressure to material that has already been through it. PCB168 publishes FR-4, BT and ABF as its HDI material families on the HDI PCB page, with FR-4 grades Tg135 / Tg150 / Tg170 / Tg180 listed on the capabilities page. Declare the family in the same block as the buildup, not in a separate section — a buildup form and a material family are one combined question at engineering review.

Whatever depth you write to, send the RFQ to quote with both fields in the same block, so the reply can address them together.

FAQ

Does a 16 layer HDI PCB cost more than a 12 layer HDI PCB?

Not reliably, and that is the useful part of the answer. Cost on HDI tracks the buildup sequence more closely than it tracks total layer count. A 12 layer board declared 4+N+4 (N=4) carries four HDI tiers per side; a 16 layer board declared 1+N+1 (N=14) carries one. The 12 layer part is the more sequentially complex object despite the lower number. Comparing layer counts across different buildup forms tells you very little. PCB168 confirms pricing only in a written quotation, so treat this as a structural point about what drives cost, not a price statement.

How many lamination cycles does a 2+N+2 build need?

The structure tells you the shape of the answer: the core (N) is laminated as a conventional multilayer, and then each of the two HDI tiers per side is added in its own press cycle. So the sequence is core lamination followed by tier-by-tier additions, and m sets how many additions. The exact cycle count for your specific board — and how it is routed through PCB168's process — is confirmed at engineering review in the written quotation, not inferred from the notation alone.

What is the difference between 16 layer HDI rigid PCB and a 16 layer conventional multilayer?

The layer count is the same; the interconnect method and the build sequence are not. A conventional 16 layer board is laminated as one stack and interconnected largely with through-holes. A 16 layer HDI board places some of those layers in sequentially added tiers connected by laser-drilled microvias — PCB168 publishes laser drilling at 0.075mm and microvia diameter ≥0.1mm under Key Features on the HDI PCB page. Whether your design needs the HDI route is a separate decision from how many layers it has; HDI or conventional multilayer addresses it directly.

Can I get more than 20 layers of HDI?

Two published figures apply and they are not interchangeable. The HDI PCB page publishes 4–20 layers for that board type. The capabilities page publishes 1–40 layers as a general fabrication range. A layer count between 21 and 40 falls inside the general range but outside the HDI page's published band, so it is not a case where you can assume the wider number simply carries over to an HDI construction. State the layer count, state the buildup form you want, cite which published figure you are working against, and ask for confirmation in writing. Do not merge the two into a single claim.

Should I specify the buildup or let the supplier choose?

Either is defensible; leaving it silent is not. If your routing is settled, declare the form — that is what makes quotes comparable. If it is not settled, say so explicitly and ask the supplier to propose within the published 1+N+1 to 4+N+4 range and state which form they quoted. The failure mode is writing only the layer count, because that reads as a complete specification while leaving the sequence entirely to interpretation.

Does a higher m mean a better board?

No. Higher m means more sequential stages, and stages accumulate process risk and registration difficulty. The right buildup is the lowest m that your routing density and via escape requirements actually need. If you are unsure whether your density requires an additional tier, that is a legitimate engineering question to raise at contact before the RFQ is finalised, rather than something to resolve by specifying upward.