HDI PCB or Conventional Multilayer? The Decision to Settle Before You RFQ

"Density is tight, so we need HDI" is the most expensive default

Most HDI enquiries we see do not start from a decision. They start from a hunch: the layout is crowded, someone says the word HDI, and it goes into the RFQ. Then the quote comes back and the project stalls — which is exactly the pattern behind searches like *cheap hdi pcb* and *hdi pcb low cost manufacturing*. People are not hunting for a discount on HDI. They are hoping HDI can be made to cost what a conventional multilayer board costs.

It cannot, and it does not need to. HDI is a different process family, not a premium trim level. Laser-drilled microvias, sequential build-up and 2mil fine lines each add process steps that a conventional multilayer board never runs. If your board does not genuinely require those steps, paying for them buys nothing.

The useful question is not "how dense is my board" but "which specific requirement forces the HDI process". That is a judgement you can make from your own layout data before any supplier is involved, and it comes down to five inputs. Get them on one page and the answer is usually unambiguous.

The starting point is not layer count — it is finest BGA pitch and escape channels

Layer count is the number people reach for first, and it is the weakest signal in the set. A 16-layer board with nothing tighter than a 0.8mm-pitch BGA is an ordinary multilayer build. A 6-layer board carrying a 0.4mm-pitch package may not be routable at all without microvias.

What actually forces the decision is whether you can escape your densest package with the line width and via structure a conventional build gives you. Work it in this order:

1. Find the finest pitch on the board. Not the average, not the biggest part — the single tightest BGA, CSP or module footprint. That part sets the rules for the whole stackup.
2. Count the channels you need between adjacent via pads. Every signal in the inner rows of that package has to leave through a gap between plated vias.
3. Check whether that gap fits your traces. PCB168's conventional multilayer line publishes 3mil/3mil minimum line width and space with a 0.1mm minimum drill (see /en/products/multi-layer-pcb/). The HDI line publishes 2mil/2mil with 0.075mm laser drilling (see /en/products/hdi-pcb/). One mil of trace width per channel changes how many signals get out per layer.
4. See what happens if you add layers instead. If the escape works at 3mil by routing across more layers, and the extra layers stay inside the multilayer range, you have your answer without touching HDI.
5. Only if escape fails at conventional geometry does the requirement become structural — and that is the case HDI exists for.

Note what this sequence does not ask about: aggregate component count, board "complexity", or how crowded the layout looks on screen. Those feelings do not map onto a process family. Escape geometry does.

The two published capability lines, side by side

Both lines are live on the site, and the differences between them are the decision criteria. Nothing here is inferred — each figure comes from the page named next to it.

Three things in that table decide most cases.

The layer ceiling runs the opposite way to intuition. The conventional multilayer line goes to 40 layers; the HDI line stops at 20. If your build needs more than 20 layers, HDI as published on that page is not where you are heading. Very high layer count and HDI build-up are different answers to different problems, and a board needing both is a case for engineering review before you fix the stackup.

Impedance tolerance lives on two pages with two numbers. The multilayer product page states ±8%. The capabilities page states ±5%, TDR verified. That is not a contradiction to be smoothed over — it tells you the tighter figure is a site-wide capability statement while the product page reflects what a standard multilayer build carries by default. If your differential pairs need better than ±8%, say the target number in the RFQ and ask which build it applies to. Do not assume the tighter figure comes free on any stackup.

Materials split the two lines. BT and ABF appear only on the HDI page. If your design requires either, the material choice has already pulled you into the HDI process family regardless of what the escape analysis says.

Which of the five inputs pushes you where

Run your board against these five, and write the result of each into the RFQ. That single table is worth more to a quoting engineer than a paragraph describing your project.

1. Finest BGA pitch. Escape fails at 3mil/3mil → HDI. Escape works at 3mil across an acceptable layer count → conventional. Borderline → quote both, see below.

2. Board outline and layer ceiling. A fixed small outline with high pin count tends to push toward build-up, because you cannot buy routing area sideways. But if the fix is more layers and you cross 20, you leave the HDI page's published range. Outline and layer ceiling have to be read together, never separately.

3. Impedance tolerance. Needing tighter than ±8% is a reason to state the number explicitly and request confirmation against your actual stackup. It is not by itself a reason to choose HDI — controlled impedance exists on both lines — but it does mean the build cannot be quoted from a parts count alone.

4. Material. FR-4 works on both lines. BT or ABF is HDI-only per the published pages. High-frequency laminate appears on the multilayer page. Let the material requirement declare itself before you argue about vias.

5. Via-in-pad. If your fine-pitch parts require vias in pads, the HDI page is explicit that via-in-pad is filled and capped. A conventional build with unfilled vias under pads is an assembly problem waiting to happen. Needing filled and capped via-in-pad is a genuine HDI-side signal.

Five inputs, five answers. If four point one way and one points the other, the one is usually the real constraint — capability is a floor, not an average.

Three ways out when HDI turns out not to be required

Escape analysis clears at conventional geometry more often than people expect. When it does, these are the levers, in rough order of how often they work:

Add layers. The published multilayer range runs to 40, far above where most crowded 8- or 10-layer designs sit. Two more signal layers frequently resolves an escape problem that looked structural. It is not free, but it prices differently from a build-up process.

Use the full 3mil. Plenty of layouts are drawn at 5 or 6mil out of habit and then declared undense-able. Going to the published 3mil/3mil minimum on the escape layers only — not the whole board — often opens exactly the channels you were missing.

Change the escape strategy rather than the process. Staggered fanout, dog-bone pattern changes, moving a connector to free up the region under the BGA: layout moves cost engineering time and no process steps. Worth exhausting before committing to build-up.

If all three are exhausted and escape still fails, HDI is not an upsell. It is the requirement, and at that point the conversation moves to which build-up depth, which is a separate decision — see HDI PCB Cost Drivers for where those quotes differ and HDI PCB for 5G Modules, Handsets and Automotive for how application shapes the build.

When it is genuinely 50/50: quote both

Some boards sit on the line, and no amount of desk analysis settles them. The right move is not to guess — it is to send two stackups in one RFQ and ask for both to be reviewed.

What to include so this does not turn into three rounds of email:

• Both candidate stackups, each with layer count, material, copper weights and finished thickness.
• The finest pitch on the board, and which package it is.
• Impedance targets with the tolerance you actually need, plus which nets they apply to.
• Whether via-in-pad is required, and on which parts.
• Quantity for prototype and for production separately. These price differently, and per-build costs behave differently across the two — HDI PCB Prototype Quoting covers which costs never amortise.

What you get back is not just two prices, it is the engineering read on whether the conventional option is manufacturable at all for your escape. That answer is the deliverable. The file-level detail of what to send is already covered in the HDI PCB Quote Package Checklist, so it is not repeated here.

Put the decision table on page one of the RFQ

The last step is the cheapest and most often skipped. Write the five inputs and your conclusion at the top of the RFQ, before the file list:

> Finest pitch: 0.4mm BGA, 1,156 ball. Escape at 3mil: fails on inner two rows. Layer ceiling acceptable: 12. Impedance: 90Ω differential, ±7% required on 24 nets. Material: FR-4 acceptable. Via-in-pad: required on U1, U4. Conclusion: HDI, 1+N+1, pending confirmation.

Six lines. A quoting engineer reads that and knows what to price, what to question, and what to flag before tooling. Without it, the same engineer has to reverse-engineer your intent from Gerbers, and every assumption they make is a place the quote can drift from what you meant.

If you want that read before committing to a stackup, send the five inputs through Get a Quote or to engineering contact and ask specifically which side of the line your escape lands on. Where your requirement sits at the very high-density end — fine-pitch flip-chip, very fine line carriers — the boundary question is different again, and HDI PCB vs IC Substrate covers which one your RFQ is actually for. For the process steps behind a build-up board, see HDI PCB Manufacturing Process; for conventional stackup construction, Multi-Layer PCB Stackup Design Guide. Full published specifications for both lines are on Manufacturing Capabilities.

FAQ

Is HDI always more expensive than a conventional multilayer board of the same layer count?

They are different process families, so a same-layer-count comparison is not the meaningful one. HDI runs laser drilling and sequential build-up steps that a conventional board does not, and those steps do not disappear at low volume. The comparison worth making is between your two viable builds — for example a 12-layer HDI 1+N+1 and a 14-layer conventional board that achieves the same escape — which is why quoting both is the recommendation when the decision is close.

Our board is 16 layers. Does that mean HDI?

No. Layer count alone does not decide it. PCB168's conventional multilayer line publishes 4–40 layers, so 16 layers sits comfortably inside conventional range. What decides it is whether your finest-pitch package can escape at 3mil/3mil with a 0.1mm minimum drill. If it can, 16 layers is an ordinary multilayer build.

We need more than 20 layers and microvias. Which line is that?

The HDI page publishes 4–20 layers and the multilayer page publishes 4–40, so a build needing both high layer count and microvia build-up falls outside a single published range. Send the stackup for engineering review rather than assuming it fits either page — this is a case that needs confirmation before you fix the design.

Can I get ±5% impedance on a conventional multilayer board?

The capabilities page states ±5% TDR verified as a site-wide capability, while the multilayer product page states ±8%. State the tolerance you need and the nets it applies to, and ask for confirmation against your specific stackup. Whether the tighter figure is achievable depends on your layer construction and material, so it requires engineering confirmation rather than a blanket yes.

We only need microvias under two BGAs. Is that still an HDI board?

Effectively yes, in process terms. Laser drilling is a process step that gets run or not run; it is not applied per-component at no cost. But the depth of build-up matters a lot to price, and a shallow 1+N+1 covering only the layers under those packages is a very different quote from a 4+N+4. Specify which packages require it and let the build-up depth be reviewed.

Does choosing conventional multilayer mean giving up blind and buried vias?

No. The multilayer page lists blind and buried via technology as available. What the HDI line adds is laser-drilled microvias down to 0.075mm, 2mil line width, ±25μm layer-to-layer registration and filled-and-capped via-in-pad. If mechanically drilled blind or buried vias solve your routing problem, that is a conventional build with via structure, not an HDI build.

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