HDI PCB Build Class: Which Specification Decisions Are Yours, Which Belong to the Fab

!High-density multilayer HDI production panel showing dense laser microvia fields alongside large gold-plated BGA and die pad areas

Most HDI quote requests arrive with the build class already filled in. Someone has written 2+N+2 in the RFQ, and the number arrived by habit rather than by calculation. It reads like a purchasing decision, a tier you select the way you select a surface finish.

It is not. A build class is the *output* of three design facts, not an input you get to choose freely. And the three facts that determine it are facts only you have. The fab cannot back-calculate them for you, because two of the three never appear in a Gerber file.

What follows separates the HDI specification into two piles: the decisions that must come from your side before a quote means anything, and the decisions you should deliberately leave open because writing them down makes the board more expensive without making it better.

1. What "build class" actually means on a quote

The notation is a layer-sequence description, read from the outside in.

The N is the conventional core: drilled and plated as a unit before the microvia layers are added. The numbers on the outside are what gets built afterwards, one sequence at a time.

PCB168 builds HDI from 1+N+1 through 4+N+4, on 4 to 20 layers, with laser vias down to 0.075mm, line width and spacing to 2mil/2mil, layer registration held to ±25µm, on FR-4, BT or ABF material. Those figures are the published window on the HDI PCB product page, and they matter here for one reason: they define the edge of the space your back-calculation has to land inside.

The important consequence of the notation is this. Each increment on the left-hand number is not a small step. It is another full build-up sequence, which means another lamination pass, another laser drill pass, another plating pass, and another registration opportunity for error. Build class is the single largest structural cost lever in an HDI quote. Which is exactly why guessing at it is expensive.

2. Back-calculation input one: the densest BGA sets your microvia layer count

Start with the tightest component on the board, and specifically with its pitch and pin count.

The question a build class answers is mechanical: *how many rows of pins do I have to get out from under this package, and how many routing layers does that take?* A microvia layer exists to let one more ring of pins escape. When you cannot escape the field in the layers you have, you add a build-up sequence.

Two numbers drive it:

• Pitch. Pitch determines whether a trace can pass between adjacent pads at all. At coarse pitch, several traces route out on the surface layer and the escape happens without much help. As pitch tightens, the channel between pads stops fitting a trace plus its clearances, and the only way out is down — each pin ring needs its own via and its own layer to run on.
• Pin count and array depth. A large array has more rings to escape. The outer rings leave easily; the inner rings are the ones that force the build class up. What matters is not the total pin count but how many rings sit inside the point where surface escape stops working.

Fine line capability and build class trade against each other here. At 2mil/2mil, more traces fit in the same channel, so more pins escape per layer, so fewer build-up sequences are needed. A design that needs 3+N+3 at conservative line widths may resolve at 2+N+2 if it is drawn to the fine-line window. That trade is worth checking before accepting a build class, because one direction adds etch process risk and the other adds a lamination cycle.

This input is yours. The fab can read pad geometry from the Gerber, but it cannot know which packages are final, which are placeholders, or whether the 0.4mm-pitch part is a committed choice or one your team is still arguing about. Declare the densest package explicitly, by pitch and array size, and say whether it is frozen.

3. Back-calculation input two: the layer pairs that must connect set the via structure

The second input is not in the Gerber at all. It is the connectivity intent.

Two boards can have identical copper on identical layers and require different build classes, because in one the microvias merely escape the BGA into the nearest signal layer, and in the other a net has to travel from the surface all the way to an inner plane without passing through the core. Same drawing, different structural requirement.

So the question to answer is: which layer pairs must be joined by microvia, and which may be joined through the core?

That answer decides between stacked and staggered structure:

• Stacked vias sit directly on top of each other, giving a vertical column from the surface down. Compact, and the only option when routing congestion leaves no room to offset. It also concentrates thermal-cycling stress in a single column, so the interfaces have to be right.
• Staggered vias offset laterally at each level. More forgiving structurally, but consumes routing area on every intermediate layer.

Either way, the depth the connection has to reach sets the number of build-up sequences, and that is your build class. PCB168 holds registration to ±25µm specifically so that stacked and staggered columns stay aligned through the build, but the decision about *which nets need to reach how deep* is not a registration question. It is a design-intent question.

If you want the declaration language for stacked versus staggered specifically, that is covered separately in microvia structure declaration. Here the point is narrower: connectivity intent is a buyer-side input, and without it the fab is guessing at your build class.

4. Back-calculation input three: your thickness ceiling removes options

The third input often gets discovered last, which is the expensive way to discover it.

Every build-up sequence adds dielectric and copper. A higher build class is a thicker board, all else equal. So if your enclosure, connector stack, or card-edge slot fixes a finished thickness ceiling, that ceiling silently deletes some of the build classes that would otherwise have solved your escape problem.

This is where the three inputs collide productively. Suppose the BGA escape analysis says 3+N+3, the connectivity intent confirms it, and then the mechanical constraint caps thickness below what 3+N+3 produces in the layer count you asked for. Now something must give, and the options are all design-side:

• reduce the core layer count so the total fits,
• move to finer line width so fewer build-up layers are needed,
• relax the thickness ceiling,
• or change the package.

None of those are the fab's call. All of them are cheaper to make now than after tooling.

Declare the thickness ceiling as a hard number with tolerance, and say what it is driven by. "1.0mm max, set by the connector" tells an engineer something actionable. "around 1mm" does not.

5. Inside the window versus a different supplier

Once the three inputs produce a build class, check it against the published window before it goes in the RFQ. The distinction to make is not cheap-versus-expensive. It is *inside the process window* versus *outside it*.

Requirements inside these bounds are a quoting conversation: you trade build class against line width against layer count and settle on a build. Requirements outside them are not a price negotiation. A build class beyond 4+N+4 or a line width below 2mil is a different process capability, and the honest answer is a different supplier, not a higher number.

This matters for RFQ efficiency. Sending a requirement that sits outside a published window and waiting for a quote wastes a cycle for both sides. Check the window first, and if you are near an edge, say so in the RFQ and ask for confirmation before tooling rather than after.

For the broader question of how to read capability claims across suppliers, see HDI manufacturing capability tiers. For whether HDI is the right answer at all versus a conventional multilayer, see HDI or conventional multilayer.

6. Two things to leave out of the RFQ

Now the other pile. These are the specifications that buyers most often over-declare, and both make the board worse when written down.

Lamination cycle count. It is tempting to specify it, because it feels like a quality control. It is not; it is a derived process parameter. The fab computes how many press cycles your build class requires given its own sequence strategy. Two fabs can build the same 2+N+2 with different cycle counts and both be correct. Fixing the count in the RFQ removes the fab's ability to choose the sequence with the fewest registration risks, and you pay for the constraint without gaining anything. Declare the build class and the structural requirement; let the fab report its cycle count back to you.

Specific stackup arrangement. Same logic, stronger effect. If you dictate which dielectric sits where and how thick each layer is, you have taken over the impedance solution, the symmetry balance, and the material availability decision all at once. The fab now builds exactly what you drew, including any impedance error in it, and including a dielectric that may be on long lead time when an equivalent sits in stock.

The productive alternative: declare the *functional* constraints — impedance targets with tolerance, thickness ceiling, layer-to-layer connectivity, material class — and require the fab to return its proposed stackup for your approval. You keep the veto, they keep the optimisation, and the stackup that comes back is one they can actually build repeatably.

Two caveats. First, if a previous build is already qualified and you need bit-for-bit repeatability, then fixing the stackup is correct — that is change control, not over-specification. Second, none of this means skipping material declaration; base material class genuinely is yours to set, and the reasoning is in HDI base material declaration.

7. How to write the RFQ

Putting the split into a request that returns a comparable quote:

Declare (yours):

1. Densest package: pitch, array size, pin count, and whether it is frozen.
2. Layer pairs that must be microvia-connected, and any that must not pass through the core.
3. Finished thickness ceiling with tolerance, and what drives it.
4. Impedance targets with tolerance, per net class.
5. Base material class and why (thermal, electrical, or assembly driven).
6. Your back-calculated build class, stated as a proposal rather than a fixed requirement.

Request back (theirs):

1. Confirmed build class, with the escape analysis that supports it.
2. Proposed stackup: layer order, dielectric thicknesses, copper weights.
3. Lamination cycle count implied by that build.
4. Via structure per span: stacked or staggered, with reasoning.
5. Line width and spacing they will actually run, against your 2mil-window assumption.
6. Any parameter sitting at the edge of the published window.

Framing your build class as a proposal is the part that pays. If your analysis says 2+N+2 and the fab's says 1+N+1 at finer line width, you have found a lamination cycle's worth of cost before tooling. If the fab says 3+N+3, you have found an escape problem your analysis missed. Neither outcome is available when the RFQ states the build class as non-negotiable.

Send these inputs through the quote request and ask for the return list explicitly. A quote without the proposed stackup and cycle count is not comparable against another quote, because you cannot see what each one assumed.

8. FAQ

Is a higher build class always better?

No. Each increment adds build-up sequences, cost, and registration risk. The correct build class is the lowest one that solves your escape and connectivity requirements inside your thickness ceiling. Specifying higher than needed buys risk.

Can I let the fab choose the build class entirely?

Partly. The fab can back-calculate from Gerber geometry, but it cannot know which packages are frozen, which layer pairs must avoid the core, or what your thickness ceiling is. Withhold those and you get a build class based on assumptions. Declare them and the fab's calculation is trustworthy.

How do fine line width and build class trade off?

Finer lines let more traces escape per layer, which can reduce the microvia layers needed. A design at 3+N+3 with conservative widths may resolve at 2+N+2 at 2mil/2mil. One direction adds etch process demand, the other adds a lamination cycle. Ask for both options priced.

What does any-layer change about this?

Any-layer removes the fixed-core assumption, so connectivity intent stops constraining which pairs are reachable. It does not remove the other two inputs: escape analysis still sets routing layer count, and the thickness ceiling still applies.

Should I specify stacked or staggered myself?

Declare the requirement that drives it — the layer pairs that must connect and any routing congestion that blocks lateral offset — and let the fab propose the structure. If a prior qualified build fixed it, specify it as change control and say so.

9. Next step

Run the three inputs before the RFQ goes out: the densest package with its pitch and frozen status, the layer pairs that must connect by microvia, and the thickness ceiling with what drives it. Back-calculate a build class, check it against the 4–20 layer, 1+N+1 to 4+N+4, 2mil/2mil, 0.075mm published window, then send it as a proposal with the return list from section 7.

Start from the HDI PCB product page to confirm the window, and submit through the quote request with the six declarations attached.