HDI PCB Incoming Acceptance: What You Cannot Verify at Receipt | PCB168

The mistake that starts it

Most incoming inspection plans for HDI boards were not written for HDI boards. They were inherited from conventional multilayer work, where the plan was adequate because the risk and the inspectable surface largely overlapped. On a conventional eight-layer board, if the outer layers look right, the dimensions are right, the mask registration is right, the finished thickness is right, and the netlist test passes, you have genuinely covered most of what can go wrong.

Carry that same plan to an HDI build and the arithmetic quietly breaks. The plan still passes or fails boards, so it still feels like acceptance. What changed is the overlap: on HDI, the attributes that decide whether the board survives assembly and field life are mostly not on the surface and mostly not reachable by any non-destructive check you can perform on a receiving bench.

The practical consequence is not that you should inspect harder. It is that a portion of HDI acceptance cannot be an inspection decision at all. It has to be a purchasing decision, made before the order is placed, about what evidence will accompany the shipment and what you are agreeing to accept without verification.

What you genuinely can verify at receipt

Keep this list, because it is real and it is worth doing. With no equipment beyond what a receiving function normally has, and with the board in hand, you can confirm:

• Surface and cosmetic condition. Mask coverage and adhesion, legend legibility, surface finish appearance and uniformity, handling damage, contamination, scratches that cross conductors.
• Outline and mechanical features. Board outline against the drawing, cutouts and slots, mounting hole positions, array format and rail layout, depanel features, edge condition.
• Finished thickness and overall profile. Thickness at defined measurement points, obvious bow and twist against the flatness requirement on the drawing.
• Exposed pad geometry. Pad sizes and shapes where they are visible, visible annular ring on through holes, visible registration of mask apertures to pads.
• Marking, labelling and packaging. Date code, lot identity, part and revision marking, barcode or QR content, moisture barrier bag integrity, desiccant and indicator condition, vacuum seal intactness.
• Electrical continuity to the declared netlist. Open and short detection against the netlist supplied with the order, where testing was specified and the report is supplied.
• Documentation completeness. Whether the documents you asked for actually arrived, in the format you asked for, referencing the lot you actually received.

Notice what all of these have in common: they are either on the outside of the board, or they are a document, or they are a yes/no electrical result. That is the full reach of normal receipt.

What you cannot verify at receipt, and why

The attributes below decide HDI reliability. None of them can be confirmed on an intact board at a receiving bench, and several cannot be confirmed by any non-destructive method at all.

Microvia bottom-of-hole connection quality. Whether the plated copper in the microvia has formed a sound metallurgical connection to the target pad is determined at the bottom of a hole you cannot see into. A board with a marginal connection often passes a continuity test on day one, because the connection conducts. It fails later, after thermal cycling in assembly or in the field, when the marginal interface separates. This is the single most consequential HDI attribute and it is invisible at receipt.

Stacked microvia alignment through the build. Where microvias are stacked, each level has to land accurately on the one below. Misalignment reduces the effective contact area at each interface while remaining fully conductive. Nothing on the surface tells you how well the stack is aligned; the top via opening can look perfectly centred while the stack beneath it walks.

Layer-to-layer registration margin in the sequential build. HDI boards are built in multiple lamination sequences, and each sequence introduces its own dimensional movement. What matters is not whether registration passed, but how much margin was left. A board that registered with almost no margin is a board whose next lot may not register at all. Margin is a process fact, not a surface feature.

Via fill and cap integrity. Filled and capped vias can contain voids, incomplete fill, or a cap that is sound in appearance and hollow underneath. A capped via that looks flat and plated on the surface tells you nothing about the column beneath it. Where components sit on via-in-pad, the void you cannot see becomes the solder defect you will see at assembly.

Consistency of the laminate and prepreg across build-up layers. HDI build-ups frequently mix materials and prepreg constructions between sequences. Whether the material actually used in each sequence matches what was specified is a traceability question, not an inspection question. No examination of the finished board will tell you which prepreg went into the third lamination.

Plated copper thickness in the microvia barrel. Surface copper thickness can be inferred reasonably well. Copper thickness on the wall of a microvia, which is where thermal-cycling stress concentrates, cannot be inferred from the surface at all.

Cleanliness of internal interfaces and absence of entrapped process residue. Residues trapped between sequences do not express themselves as a visible defect. They express themselves as delamination under thermal load.

Why the window closes at assembly

There is a timing fact buried in this that costs buyers money, and it has nothing to do with inspection technique.

Every unverifiable attribute above lives inside the board, and the only way to examine most of them is to destroy the board: cross-section it, microsection the specific via of interest, and look at the interface. That requires a board you are willing to sacrifice and a board that still represents the lot.

After assembly, neither condition holds easily. The board now carries components, so the interesting via may be underneath a BGA. It has been through reflow, so any thermal damage you find may have been caused by reflow rather than fabrication, and you can no longer tell which. If the board failed in the field, it has also accumulated operating stress. At that point the honest answer to "was this a fabrication defect or an assembly defect?" is usually that the evidence to distinguish them no longer exists.

So the decision point is not receipt and it is certainly not failure analysis. It is the order. Either the lot ships with evidence created while the evidence was still creatable, or that evidence is gone permanently and the question will later be settled by commercial negotiation rather than by fact.

Four release mechanisms, and what each one costs you

For every unverifiable attribute, you have exactly four options. Each is legitimate. None is free.

1. Release on supplier report, per lot. The supplier performs the measurement or examination as part of their process and ships the result with the lot. Cost: you pay for the reporting, and you are trusting the supplier's own measurement. Suitable for: registration margin, material identity per sequence, plating thickness data, electrical test results. This is the default for most attributes and the cheapest meaningful evidence.

2. Release on coupon microsection. The panel carries a test coupon designed to represent the build, the coupon is sectioned, and the section is examined and reported. Cost: panel area, coupon design effort, sectioning and reporting time, and a real limitation — the coupon represents the panel, not the specific board you received. Suitable for: microvia bottom-of-hole connection, stack alignment, barrel copper, fill and cap integrity. This is the only practical evidence for the attributes that matter most, which is why coupon requirements belong in the RFQ rather than in a later argument.

3. Release on tightened electrical specification. Instead of plain open/short testing, specify the test conditions that make marginal connections show up: resistance measurement against a declared threshold rather than pass/fail continuity, or testing after a thermal preconditioning sequence. Cost: test programme development, longer test time, and a higher measured reject rate that you will be paying for one way or another. Suitable for: catching marginal interconnect that plain continuity passes.

4. Accept without verification. Explicitly agree that an attribute will not be verified, and that the commercial consequence of a failure attributable to it is handled by a stated remedy. Cost: you carry the risk. Suitable for: low-consequence attributes, prototype and early development builds where speed dominates, and genuinely any attribute where the cost of evidence exceeds the cost of the failure.

The fourth option is not a failure of diligence. Pretending you are in option 1, 2 or 3 when you never specified it — that is the failure. A buyer who has knowingly chosen option 4 for a prototype lot is in a far better position than a buyer who assumed coupons were standard and discovers at the dispute stage that they were never ordered.

Writing it into the RFQ

Here is the part that converts all of the above into something actionable. For each unverifiable attribute, the RFQ needs to state four things: who declares the requirement, what evidence releases it, when that evidence is produced, and what happens if the evidence is absent or adverse.

Concretely, for an HDI order, declare:

• Microvia connection evidence. Whether coupon microsection is required, at what frequency relative to lots, which via structures the coupon must represent, whether the report includes images, and whether the coupon is retained or consumed. If you do not require it, say so explicitly rather than leaving it unsaid.
• Registration and build evidence. That the supplier reports registration results per lot, not merely that registration was "within specification", so that margin trend is visible across reorders.
• Material traceability per sequence. That the laminate and prepreg actually used in each lamination sequence are reported against the approved stackup, with a declaration format you can read — IPC-1752A class data where applicable, or a stated equivalent.
• Via fill and cap requirements. The intended function (via-in-pad under components, thermal, plugged for assembly) stated as a function rather than as a process, so the supplier specifies the process that achieves it and reports against it.
• Electrical test definition. Whether the test is continuity-only or resistance-based, against which netlist revision, and whether any preconditioning applies. The netlist revision matters more than buyers expect; a test against the wrong revision is a passed test that proves nothing.
• Acceptance standard and class. Which standard governs, at which class, with any deviations named. Naming IPC-6012 and IPC-6016 for the fabrication and the HDI build respectively, with class stated, prevents the common situation where two parties agree on "IPC standard" and disagree on everything that follows.
• Evidence retention and access. How long the supplier retains lot records and retained coupons, and whether you may request examination later. An attribute can be unverifiable at receipt and still be verifiable at month three, provided someone kept the coupon.
• Moisture and handling at the interface. HDI boards with thin dielectrics are moisture-sensitive; declare the bag, desiccant, indicator and floor-life expectation per J-STD-033 and state who owns the consequence of a compromised bag. This is one of the few internal-risk items you can actually see evidence for at receipt, and it is routinely left unstated.

What the receiving function should actually do

Given all of this, a realistic HDI receiving procedure has three parts, and the third is the one usually missing.

First, perform the verifiable checks properly, and record them. They are not the whole risk but they catch real defects, and the record is what lets you distinguish incoming condition from in-house handling damage later.

Second, verify the documents as a deliverable in their own right. Did the coupon report arrive? Does it reference this lot? Does the material declaration match the approved stackup? Is the netlist revision the one you released? A missing or mismatched document is a hold condition, and it is a condition the receiving function can detect without any board-level capability at all. This single discipline recovers most of the value of everything specified in the RFQ.

Third, do not record a pass on attributes you did not verify. If the acceptance record says the lot was inspected and accepted, and the unverifiable attributes are silently inside that "accepted", you have destroyed your own position for any later claim. The acceptance record should state what was verified, what was released on supplier evidence, and what was accepted without verification. That is not bureaucratic caution; it is the document that decides who pays when a board fails in month four.

When something does fail: the order of evidence

If a failure appears after assembly, the evidence hierarchy runs roughly as follows, strongest first: a retained coupon from the same panel, sectioned and examined; the supplier's lot records for that panel; a sacrificial sibling board from the same lot, unassembled, sectioned; the failed assembled board itself, sectioned, with the acknowledged ambiguity that reflow stress is now in the picture; and finally, nothing but argument.

Each step down that list costs you leverage. The whole purpose of specifying evidence at RFQ stage is to keep yourself near the top of it. Buyers who skip the specification and later demand failure analysis are asking the supplier to produce evidence that neither party preserved, and the outcome of that conversation is determined by commercial relationship rather than by engineering fact.

Bringing it together

HDI acceptance has a structural asymmetry that conventional multilayer acceptance does not: the inspectable set and the risky set barely overlap. You cannot close that gap by inspecting more carefully, because the gap is physical. You close it by deciding, before the order, which unverifiable attributes get supplier reporting, which get coupon evidence, which get a tightened electrical specification, and which you knowingly accept unverified — and then by writing all four categories into the RFQ with the retention terms that keep the evidence available after the boards have shipped.

If you are preparing an HDI order and want the evidence requirements reviewed against the build you actually need, our HDI PCB capability page sets out the build options, and the quote request accepts the stackup and acceptance requirements together so the evidence terms are settled before the first lot runs. For the broader manufacturing scope behind those terms, see our capabilities overview.

Related reading on specifying the individual declarations referenced above: filled and capped via-in-pad declarations in the RFQ, HDI build class specification and decision ownership, stacked versus staggered microvia structure declarations, layer registration and annular ring tolerance, and the general incoming inspection and acceptance plan for PCB delivery.

FAQ

Can X-ray inspection replace coupon microsection for HDI?

Not for the attribute that matters most. X-ray is genuinely useful and non-destructive, and it will show you gross voiding, obvious misregistration and large fill defects. What it does not resolve is the quality of the metallurgical interface at the bottom of a microvia, which is the dominant HDI failure mode. Treat X-ray as a useful screen that reduces how often you are surprised, not as a substitute for the one method that can see the interface.

If the netlist test passed, is the interconnect sound?

No, and this is the most expensive misunderstanding in HDI acceptance. A marginal microvia connection conducts. It will pass continuity testing on the day it is tested and separate later under thermal cycling. If you need confidence in interconnect integrity rather than interconnect existence, you need either resistance-based testing against a declared threshold, testing after thermal preconditioning, or coupon evidence. Plain open/short testing answers a different question than the one you are asking.

Who should own the coupon design?

The supplier should design the coupon, because the coupon has to represent their actual build sequence, and only they know it. The buyer should own the requirement: which via structures must be represented, how often coupons are sectioned relative to lots, what the report must contain, and whether coupons are retained. Buyers who try to design the coupon themselves usually produce one that does not represent the sequence; buyers who leave the requirement entirely to the supplier usually get no coupon.

Our volumes are small. Is coupon evidence proportionate?

Often not, and that is a legitimate conclusion. For prototype and early development builds the right answer is frequently to accept several attributes unverified and move fast. The requirement is not that you buy coupons; it is that you decide consciously and record the decision. The thing to avoid is reaching production volume still running the prototype evidence regime because nobody revisited it — transition points are where this bites.

What is the minimum we should specify if we only change one thing?

Two things, and they are cheap. First, require that documents referencing the correct lot and the correct netlist revision arrive with the shipment, and treat a document mismatch as a hold. Second, require a stated evidence retention period with access rights, so that an attribute you could not verify at receipt is still verifiable in month three if a problem appears. Together these cost very little and they move you from arguing to checking.

Can we add coupon requirements to a reorder of an existing part?

Yes, but expect it to be priced and scheduled as a change rather than absorbed. Coupons consume panel area, which changes panel utilisation, which changes unit cost; and the sectioning and reporting is labour. Raise it as a change to the acceptance terms rather than as an inspection request, and raise it before the panel is laid out, not after.

Does a higher acceptance class solve this by itself?

It helps and it does not close the gap. Specifying a class raises the criteria that get applied where examination happens, which is valuable. It does not create the examination. A class designation with no coupon requirement and no reporting requirement still leaves the internal attributes unverified; it just means that if anyone ever does look, they will judge against a stricter rule. Class and evidence are separate decisions and both need stating.

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