Via-in-Pad on HDI PCB: Filled and Capped Are Two Different Declarations

The four words that decide four things

Open the PCB168 manufacturing capabilities page, find the HDI block, and the

via-in-pad row says exactly this: Filled and capped. Four words. Most buyers read them as a

single yes/no feature and tick a box in the RFQ that says via in pad: yes.

Those four words are not one feature. They describe **two sequential process steps plus one

acceptance property**, and each one answers a different question:

Write via in pad: yes and you have answered none of the three. You have delegated all of them

to whoever reads your RFQ, and they will resolve each one with a house default. House defaults are

not wrong, but they are theirs, not yours, and they will not appear in the quote as line items you

can compare between suppliers.

Step one: fill — resin or conductive, and why the choice is not cosmetic

Filling a via in a pad closes the barrel so that solder paste cannot drain into the hole during

reflow. That is the baseline reason, and it applies to every via-in-pad regardless of function.

Beyond that baseline, fill splits into two families, and the deciding question is **whether that via

is part of an electrical or thermal path**:

• Non-conductive (resin) fill closes the barrel mechanically. The plated barrel wall still

carries the signal, exactly as it did before filling. This is the normal choice for signal

via-in-pad under a BGA, where the via exists to escape a pad to an inner layer and nothing more.

• Conductive fill puts a conductive medium in the barrel itself. Buyers reach for it when the

via sits in a thermal pad or a current-carrying pad and they want the barrel volume contributing,

not just the plated wall.

The practical RFQ consequence: conductive fill is a different material and a different process step

from resin fill, so it is a different cost and a different qualification. If you do not say which

family you need, you will be quoted the one the supplier runs as standard — and if your board has

both kinds of pads, one of the two groups will be built wrong for its purpose.

There is a second reason to be explicit. The /en/capabilities/ quality control block lists

X-Ray inspection as covering "BGA and via fill verification". Fill quality is an inspected

property on this line, not an assumed one. But inspection can only verify against a stated

requirement. Declare the fill type and you get a verifiable build; leave it blank and there is

nothing specific to verify against.

Step two: cap plating — why "filled" does not mean "solderable"

This is the step most RFQs skip, and it is the one that most often shows up as an assembly problem

rather than a fabrication problem.

After a via in a pad is filled, the fill material occupies the barrel — but the pad surface is now a

copper annulus with a non-copper disc in the middle. You cannot reliably reflow a fine-pitch BGA

ball onto that. Cap plating is the separate step that plates copper over the filled barrel

opening so the pad becomes a continuous, uniform copper surface, and only then does it behave like

an ordinary SMD pad.

So the sequence is: plate the barrel → fill it → plate over it → then apply surface finish. The

surface finish declaration sits

*downstream* of cap plating and cannot compensate for its absence. ENIG on an uncapped filled via

still leaves you with a discontinuous pad.

Why buyers miss this: because Filled and capped reads as one phrase, and because on a datasheet

both words live in the same table cell. In the RFQ they must be two separate statements, because

there are legitimate builds where a via is filled but *not* capped — a via in a non-component area,

filled only to support a later lamination cycle, has no reason to be capped. If your RFQ does not

distinguish, you cannot tell whether your quote includes cap plating on the pads that need it.

Step three: pad flatness — the one that decides assembly yield

Here is the part that is genuinely counterintuitive. A via can be correctly filled and correctly

capped and still fail at assembly, because **fill and cap are process declarations while flatness is

an outcome property**.

Filling and capping leave a surface that can end up slightly dished (a shallow depression over the

former barrel) or slightly domed (a bump). Either deviation is invisible in a normal incoming

inspection of the bare board and both of them matter at exactly one moment: when a fine-pitch BGA

is placed and reflowed. A dished pad holds less paste under the ball than its neighbours; a domed

pad holds the ball higher. Across a large ball count, that variation is what turns into open joints

and head-in-pillow defects.

The reason this must be declared separately: **"filled and capped" is a statement about what was

done, not a statement about how flat the result is.** A supplier can satisfy both process words

completely and still hand you a board whose via-in-pad surfaces vary more than your BGA pitch can

tolerate. If flatness is a requirement for your build, it has to appear in the RFQ as its own

acceptance item, with a stated inspection method — and for HDI work, it should be agreed before

tooling, not discovered at first article.

PCB168 holds layer-to-layer registration at ±25μm and laser-drills microvias down to 0.075mm on

HDI builds of 4-20 layers with 1+N+1 to 4+N+4 stackups. Those are stated

capability windows. Pad flatness after fill and cap is a different axis entirely, which is exactly

why it needs its own line in the RFQ rather than being inferred from the registration or microvia

numbers.

Which pads — because the answer is almost never "all of them"

The fourth decision hiding in via in pad: yes is scope.

Via-in-pad is a solution to a routing density problem. It is worth its process cost under a

fine-pitch BGA, in a thermal pad, or anywhere a pad has nowhere to escape to except straight down.

It is not worth it on a pad that has room for a conventional dog-bone escape, and applying it board-

wide multiplies a process cost across pads that did not need it.

So the RFQ should group pads, not blanket the board:

• fine-pitch BGA / CSP escape pads — via-in-pad, resin fill, capped, flatness controlled
• thermal / power pads — via-in-pad, fill family stated according to whether barrel conduction is

wanted, capped

• vias in non-component areas — filled if a later lamination cycle requires it, capping not required
• pads with conventional escape routing — no via-in-pad

Stating it this way does two things: it stops you paying for capability on pads that do not need it,

and it makes the comparison between two quotes meaningful, because both suppliers are now pricing

the same grouped requirement instead of two different interpretations of the word "yes".

What goes in the RFQ

Six fields. Each one maps to a decision above:

1. Scope — which pad groups get via-in-pad, identified by reference designator or net, not "all".
2. Fill type per group — resin (non-conductive) or conductive, with the reason stated (structural

closure vs. electrical/thermal path). The reason matters: it lets the supplier flag a mismatch.

1. Cap plating per group — required or not required. Do not leave this to be read out of the

word "filled".

1. Flatness requirement — stated as its own acceptance item for the fine-pitch groups, with the

inspection method you expect, and confirmed before tooling.

1. Fill verification expectation — /en/capabilities/ lists X-Ray for BGA and via fill

verification; state whether you want that evidence reported and at what stage.

1. Interaction with surface finish and microvia structure — name the surface finish separately,

and name the microvia structure (stacked or staggered) separately. Both are different fields with

different owners.

What to settle before tooling and what can wait

Not everything has equal urgency, and treating it all as equally urgent is how RFQs stall.

Before tooling — scope, fill type, and cap plating. These three change the process plan and the

tooling. Changing them after tooling means re-tooling, and on an HDI build with multiple lamination

cycles that is not a small change. Flatness belongs here too, because it may influence how the

supplier sequences fill and plating.

Can be settled at first article — the reporting format for fill verification, and the sampling

plan for flatness measurement. These are evidence and documentation questions. They should be agreed

before production release, but they do not gate tooling, and holding the RFQ open for them costs you

schedule for no benefit. Where they do need to be nailed down is in the

quote package, so that nothing is renegotiated later.

Where this sits next to the other HDI declarations

Via-in-pad is one field among several, and the common failure is to let one field's answer silently

imply another's:

• Microvia structure (stacked or staggered) is a separate declaration — see

HDI microvia structure in an RFQ.

A stacked structure does not tell the supplier anything about whether you want the top pad capped.

• Aspect ratio and core thickness constrain what is drillable and platable — see

HDI aspect ratio and thin core limits.

• Layer count and lamination cycles determine how many times a filled via gets pressed — see

HDI layer count and lamination cycles.

This is the one place via fill genuinely couples to another field: a via that will see additional

lamination cycles may need filling for reasons that have nothing to do with pad solderability.

• Surface finish is applied after capping and cannot substitute for it.

Get the four via-in-pad decisions written down and the rest of the HDI RFQ gets easier, because you

stop having the same conversation four times under four different headings. If you want the build

confirmed before tooling, send the stackup, the pad groups and the pitch of your tightest BGA

through Get a Quote and ask for the via-in-pad treatment to be quoted per group.

FAQ

Is via-in-pad the same as via filling?

No. Via filling is one step of it. Via-in-pad means a via is placed inside a component pad, which

then requires the barrel to be filled so paste cannot drain into it, and usually requires cap plating

so the pad is a continuous copper surface. A via can be filled without being in a pad, and a via in a

pad that is filled but not capped is still not reliably solderable.

Do I need conductive fill, or is resin fill enough?

The deciding question is whether you want the barrel volume to participate in an electrical or thermal

path. For a signal via escaping a fine-pitch BGA pad to an inner layer, the plated barrel wall already

carries the signal and resin fill is the normal choice. Conductive fill is what buyers specify when the

via sits in a thermal or current-carrying pad. State the intent in the RFQ, not just the material — it

lets the supplier flag a mismatch before tooling.

If the capability sheet already says "filled and capped", why declare it again?

Because the capability sheet states what PCB168 can do, while your RFQ states what your board needs on

which pads. Capability is a window; a declaration is a commitment. Without the declaration, scope, fill

family, capping and flatness all get resolved by house default, and none of those defaults appear in the

quote as comparable line items.

Does the surface finish fix a pad that was not cap plated?

No. Surface finish is applied after cap plating and follows whatever surface it is given. ENIG over an

uncapped filled via still leaves a discontinuous pad. Declare capping and surface finish as two separate

fields; see the surface finish declaration guide for how the finish choice interacts with fine-pitch

assembly.

How is pad flatness verified, and when should I raise it?

Flatness is an outcome property rather than a process step, so it needs its own acceptance item with an

agreed inspection method, raised before tooling because it can influence how fill and plating are

sequenced. /en/capabilities/ lists X-Ray inspection covering BGA and via fill verification, plus

cross-section analysis for quality validation; agree which evidence you want reported and at what stage.

Related links

• Manufacturing Capabilities
• HDI PCB