HDI PCB Aspect Ratio and Thin Cores: Why Adding Layers Is Sometimes Cheaper Than Going Thinner

Two savings ideas that cancel each other out

An HDI RFQ usually arrives with two targets attached. One is a finished thickness, because the board has to fit an enclosure, a connector stack, or a card slot. The other is a layer count, because layers look like the line item you can cut.

Buyers treat both as savings in the same direction. Fewer layers, less material, thinner board, lower price. On a two- or four-layer board that intuition mostly holds. On HDI it stops holding, and it stops for a reason that never shows up on the quote sheet: thickness is not a free variable. It sets the aspect ratio of every through-hole on the board, and it sets how thin the internal cores have to be.

Both of those are process limits, not material limits. When you push them, cost moves from the material line to the process line — and the process line is where yield risk lives.

Aspect ratio: the ratio your enclosure quietly chose for you

Aspect ratio is the drilled depth divided by the drilled diameter. For a plated through-hole that spans the whole board, the depth is the board thickness. So the ratio is set by two numbers you usually decide in different meetings:

• Board thickness — decided by mechanical, from the enclosure.
• Smallest through-hole diameter — decided by layout, from the densest part of the routing.

Neither decision mentions the other. Together they produce a number the fabricator has to plate into.

Why plating cares: copper has to be deposited evenly down the full length of a hole from both ends. The deeper and narrower the hole, the harder it is to get solution exchange and current distribution into the middle of the barrel. Thin plating at mid-barrel is the classic failure, and it is the kind that passes a visual check and fails later under thermal cycling.

Now notice the direction of the trap. Making the board thinner reduces depth, which helps the ratio. But buyers rarely thin the board in isolation — they thin it *while* keeping the same dense routing that needs small holes, and often *while* removing layers, which forces the remaining layers to carry more routing and therefore need *smaller* holes. The denominator shrinks faster than the numerator. The ratio gets worse, not better.

PCB168's published capability set is the frame to check this against: minimum drill 0.1mm mechanical / 0.075mm laser, board thickness 0.2mm - 6.0mm (/en/capabilities/). Those are the endpoints of each axis independently. They are not a promise that any thickness pairs with any diameter. The pairing is what you have to ask for, and it is the single most common thing missing from an HDI RFQ.

> Do not let a supplier answer this with a single number. A bare aspect-ratio figure with no stated hole diameter and no stated thickness is not a capability statement. Ask for the ratio *and* the conditions it holds under, and ask for it in writing on the specification, the way /en/products/hdi-pcb/ states Registration ±25μm as a bounded, conditioned figure.

Thin cores: where "thinner" turns into a handling problem

The second constraint is less intuitive. To hit a low finished thickness with a given layer count, the internal cores and the prepreg between them all have to get thinner. That is arithmetic, not engineering judgement.

Thin cores change what the shop floor is doing:

• Handling. A very thin core is mechanically floppy. It has to be moved, imaged, etched, and registered without distortion. Every one of those steps had margin when the core was rigid.
• Registration. Slack material moves. Layer-to-layer alignment gets harder exactly when the design can least afford it. Registration is a published, bounded figure on PCB168 capability pages (Layer-to-Layer Registration ±25μm), and the etch side of the same squeeze is covered in HDI fine line etching RFQ inputs.
• Dielectric margin. Thinner dielectric between copper layers means less room for any local variation, and it interacts with impedance targets. PCB168 publishes impedance control at ±5% (TDR verified) (/en/capabilities/) — that tolerance has to be achieved *with* whatever dielectric thickness your build forces.

The practical consequence: below some thickness, for a given layer count, the build stops being a material question and becomes a "can this be handled reliably" question. Suppliers price that as risk. You will see it as a higher unit price, a longer lead time, a request to relax a tolerance, or a quote that simply comes back with a thickness counter-proposal.

Why adding layers can be the cheaper build

Here is the reversal. Adding two layers does three things at once:

1. It gives routing somewhere else to go, so the densest area no longer needs the smallest possible hole. The aspect-ratio denominator grows.
2. It lets each core stay thicker for the same finished thickness budget — or lets you accept a slightly thicker board with comfortable cores instead of a target-thickness board with marginal ones.
3. It can let you drop a microvia level. If routing relief means you no longer need to go from 2+N+2 to 3+N+3, you have removed a sequential lamination step. That step is one of the larger discrete costs in an HDI build, and it is documented from the layer-count side in HDI layer count and lamination cycles in the RFQ.

Against that, two extra layers cost: two more copper layers of material, and whatever the added stackup symmetry work requires. That is a known, linear, quotable cost.

What you avoided is process risk — marginal plating, difficult registration, handling scrap. Process risk is not linear and it is not fully quotable in advance. It shows up as yield, and yield shows up as either price padding or a bad delivery.

So the comparison is not "more layers vs fewer layers." It is:

The third row is why this cannot be answered from a rule of thumb. You need to know which constraint was actually binding on your board before you know which direction saves money. That is a question for the supplier's process window, not for a blog post.

The four numbers to settle before the RFQ goes out

None of these require you to disclose anything sensitive, and all four are answerable by your own mechanical and layout owners.

1. Finished thickness: target, tolerance, and whether it is hard.

State the number *and* state whether it is a hard mechanical limit or a preference. "1.0mm" and "1.0mm because it seats in a 1.1mm slot" get different responses. If it is a preference, say what range is acceptable. This one field prevents most of the wasted quote cycles.

2. Smallest through-hole diameter, and where it is.

Not the smallest via anywhere — the smallest hole that has to span the full board. A blind via that only goes two layers deep has a completely different ratio than a through-hole at the same diameter. If the small holes are all in a localised dense region, say so; that is exactly the information that lets a supplier suggest relief.

3. Layer count: fixed, or an outcome?

If layer count is an output of "whatever routes cleanly," say that. It opens the trade. If it is fixed for a reason — a signal-integrity plan, a reused stackup, a qualified design — say the reason. A supplier who knows the constraint is real will stop proposing to change it and price the harder build instead.

4. Whether the finished thickness includes surface finish and any copper build-up.

Ambiguity here produces boards that are technically in spec and mechanically wrong. State the measurement basis. PCB168's published surface finish options are HASL, ENIG, OSP, Immersion (/en/capabilities/) and they are not thickness-neutral relative to each other.

What to ask the supplier, and how to grade the answer

Ask exactly this: *"For a finished thickness of X with a minimum through-hole of Y, what is your plated through-hole aspect ratio limit, and what is the minimum core thickness in the stackup you would propose?"*

Grade the reply:

• Full answer — a ratio, the conditions it holds under, and a proposed stackup with core thicknesses. This is a supplier engaging with your board. Get it onto the specification document.
• Ratio only, no conditions — incomplete. A ratio without a diameter and a thickness is not a commitment. Ask again with the conditions named.
• "We meet IPC" — a floor, not a capability. IPC-6012 and IPC-6016 define acceptance classes; a class reference tells you what the board will be judged against, not what this shop can build. Both belong in the RFQ, and neither substitutes for the process window.
• "No problem" — zero information. Treat it as unanswered.
• A thickness counter-proposal with reasoning — often the best outcome available. It means the supplier found the binding constraint and is telling you where it is.

Escalation path: if a design is genuinely at the edge of what makes sense as a laminated board, that boundary is a separate conversation — see HDI board or IC substrate: where the RFQ boundary sits.

Before quoting vs. during DFM

Split the work so you are not blocking a quote on detail that can wait.

Before quoting — the four numbers above, plus whether blind/buried vias are in play. Enough to price and to catch an impossible combination early. If you want the full submission set, the HDI quote package checklist covers what else travels with it.

During DFM — the specific stackup, per-layer dielectric thicknesses, exact core selection, impedance modelling against the proposed stackup, and the final drill table. This is where the supplier's proposal meets your signal-integrity requirements. Material choice interacts here too; HDI base material FR-4, BT and ABF in the RFQ covers that axis, and PCB168 lists FR-4/BT/ABF for HDI on /en/products/hdi-pcb/.

When quotes for "the same board" diverge

If two suppliers quote the same layer count and thickness at very different prices, the gap is usually not margin. It is a different assumption about what has to be achieved.

Check, in order: the aspect ratio each one assumed; the core thicknesses each one proposed; whether one of them silently assumed a thicker finished board; whether one added a lamination cycle the other did not. The cheaper quote may be pricing a build that does not meet your mechanical constraint, or may be assuming a hole diameter larger than your layout actually has. Cheap HDI quotes and build-assumption checks walks the general version of this comparison; the thickness-specific version is: make both suppliers state the thickness and the minimum through-hole they priced against, then compare those two lines before you compare the prices.

Send the resolved numbers with your files through the PCB168 quote form, and check the published HDI figures on the HDI PCB product page and the full capability list before you assume a combination is available.

FAQ

Does a thinner HDI board always cost more?

No. Thinner costs more only when it pushes a process limit — aspect ratio or core handling. A thinner board that stays inside both limits is often unchanged in price or slightly cheaper on material. The cost appears at the limit, not gradually.

How do I know if aspect ratio is my binding constraint?

Find the smallest hole that spans the full board and pair it with your target thickness. If that pairing is the thing your supplier hesitates on, it is binding. If the supplier's concern is instead about core thickness or registration, the binding limit is thin-core handling. Ask which one it is; suppliers will usually tell you directly.

Why not just use blind vias instead of through-holes to fix the ratio?

That is often the right move, and it is what HDI is for. But blind and buried vias may add a lamination sequence, which has its own cost, and the structure has to be declared properly. See microvia structure: stacked vs staggered declaration.

Can I ask for a specific core thickness?

You can, and you should if signal integrity requires it. Understand that fixing core thickness and finished thickness and layer count simultaneously may leave no valid solution. Fix the two that matter and let the third move.

Is adding layers always safe?

No. More layers mean more copper to balance and more layers to register. It is a better-understood cost, not a free one. And if it adds a lamination cycle, the saving can disappear entirely — which is why the layer count and lamination cycle question should be answered together.

What if my supplier just proposes a thicker board?

Take it seriously. That reply usually means they located the binding constraint. Ask which constraint drove it and by how much the thickness has to move. If the mechanical limit is genuinely hard, say so and ask what has to change instead — hole diameter, layer count, or via structure.

Sources: PCB168 published capability data on /en/products/hdi-pcb/ (4-20 layers, 2mil/2mil, laser drill 0.075mm, Registration ±25μm, stackup 1+N+1 to 4+N+4, FR-4/BT/ABF) and /en/capabilities/ (1-40 layers, min drill 0.1mm mechanical / 0.075mm laser, board thickness 0.2mm - 6.0mm, max panel 600mm × 1100mm, copper weight 0.5oz - 20oz, impedance control ±5% TDR verified, surface finish HASL/ENIG/OSP/Immersion, microvia diameter ≥0.075mm, layer-to-layer registration ±25μm, blind/buried vias, via-in-pad filled and capped). IPC-2226, IPC-6012 and IPC-6016 are referenced by standard name and acceptance class only. No aspect-ratio limit, core thickness, lamination count, yield, lead time, equipment or customer figure is asserted beyond those published pages.

Image alt: Operator station of a board processing machine on a workshop floor, with panel material staged on the worktable beside the machine body.

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