HDI PCB Fine Line Etching: RFQ Inputs That Make 2mil Quotable

Why "minimum 2mil" is not a quotable input

A minimum capability figure answers one question: *has this supplier ever achieved this geometry?* It does not answer the questions pricing depends on.

Three things are missing from a bare 2mil request:

Which layers. A 12-layer HDI build might need 2mil only on two signal layers under a fine-pitch BGA, and be perfectly comfortable at 4mil elsewhere. Quoting the whole stackup at the tightest number prices work nobody asked for.

On what copper. Line width capability and finished copper weight are coupled. The same etch process resolves finer geometry on thinner copper than on heavier copper, because more copper thickness means more material to remove and more sidewall to control. A 2mil request on a layer you have specified as heavier copper is a different manufacturing problem from 2mil on a thin inner layer — sometimes a different answer entirely.

With what tolerance. "2mil" as a design intent and "2mil ±10%" as an acceptance criterion are not the same purchase. The second one commits the supplier to a measured outcome; the first one commits nobody to anything.

Until those three are on the page, a supplier is choosing between two bad options: assume the worst case and quote high, or assume the friendly case and leave the gap to be discovered after tooling. Neither is a quote you can compare against another supplier's.

Regular fine line versus minimum capability: which one should you quote against

PCB168's HDI page lists two different fine line figures, and the distinction matters more than anything else in this article.

If your fine-pitch BGA escape closes at 3/3mil, quote 3/3mil. You get a cleaner price, a shorter engineering loop, and fewer conditional clauses in the reply. Reach for 2mil/2mil when the pad pitch, via structure and escape count leave no alternative — and when you do, say so explicitly and localise it, which is what the next section is about.

Treating the minimum figure as the default request is the single most common way fine line HDI RFQs get more expensive than they needed to be.

The five RFQ inputs a fine line HDI quote actually needs

1. Target line width and spacing, stated as a number you can accept

Write the number your design actually uses, not the tightest number the supplier advertises. If different areas differ, write the tightest value and note that it is localised — do not average.

State line width and spacing separately. They are not always equal, and a design that needs 2mil traces on 3mil spacing is a meaningfully different etch problem from 2/2.

Bad: fine line HDI, minimum line width

Usable: L3 and L10: 3mil/3mil general routing; BGA escape region only: 2mil/2mil trace and space

2. Finished copper weight on every layer that carries fine lines

This is the input most often missing, and the one that most often changes the answer. Copper weight has to be stated as finished copper, per layer, and it has to appear on the same page as the line width request — not buried in a separate stackup file that may or may not agree with the fabrication notes.

If your stackup uses different copper weights on different layers, list them. A supplier cannot confirm a fine line window against an unstated copper weight, and a design with mixed copper weights and one global line width note is a conflict waiting to surface at CAM.

3. Which layers and which regions are the tightest

Two sub-inputs, both cheap to provide:

• Layer list. Name the layers that carry the tightest geometry. L3, L10 is enough.
• Region. Say whether the tightest geometry is board-wide or confined to identifiable areas — a BGA escape, a connector fan-out, a specific footprint. A reference designator or a bounded area on a drawing is ideal.

This one input is usually the difference between a quote for a fine line board and a quote for a board with fine line areas. They are not the same product.

4. The line width deviation you can live with

Every etch process delivers a distribution, not a single value. The question a supplier needs answered is what part of that distribution you will accept.

You have three practical ways to state it, in order of usefulness:

1. A named tolerance on finished line width, applied to the fine line layers.
2. A functional constraint instead of a geometric one — for example, that the fine line pairs are impedance-controlled, which puts the acceptance on electrical performance rather than on a caliper reading.
3. A reference to the acceptance class you are buying to, citing the applicable IPC performance specification by name rather than reproducing its tables.

What does not work is silence. Silence means the supplier applies its own default, which you will only discover if something fails.

5. How fine line geometry will be verified and accepted

Decide before the quote, because verification is a cost and a schedule item, not a courtesy.

Options to pick from and state:

• Visual/AOI inspection to a stated acceptance class
• Measured line width reporting on the fine line layers
• Impedance verification where the fine lines form controlled-impedance structures
• A first-article review before the balance of the lot proceeds

Each has a different cost and lead-time consequence. Choosing in the RFQ means the quote you receive already contains it. Choosing after the quote means a revision.

Finished copper weight decides whether fine lines are feasible at all

Worth restating on its own, because it drives so many surprised responses.

Fine line etching removes copper laterally as well as vertically. The thicker the copper, the more lateral loss has to be compensated for, and the harder it is to hold a consistent trace width across a panel. The direction of the effect is not controversial: thinner finished copper widens the fine line window; heavier finished copper narrows it.

That is a directional statement, and this article deliberately stops there. The specific compensation applied for a given copper weight is process data — PCB168 confirms line width, spacing and impedance against your stackup before production rather than publishing a conversion table, and any supplier who hands you a universal copper-to-minimum-line-width chart without seeing your stackup is describing a marketing position, not a process.

The practical consequence for your RFQ: if you want the tightest geometry, check whether the layer carrying it can use the thinnest copper your current-carrying and plating requirements allow. Sometimes a copper weight change on two layers removes the need for a conditional quote entirely.

This is also the axis on which HDI and heavy copper pull in opposite directions. PCB168's heavy copper PCB page lists a minimum line width of 6mil against copper weights of 3oz and above — the same trade-off seen from the other end. If a single board needs both dense fine line routing and heavy current paths, that is a mixed-construction conversation to have before the RFQ, not after.

Narrower traces move impedance: one consequence you cannot ignore

Over-etch narrows traces, and narrower traces shift impedance. If your fine line pairs are also controlled-impedance structures, the line width tolerance and the impedance tolerance are describing the same physical outcome from two directions, and specifying them independently can produce a contradiction the supplier has to resolve for you.

State which one governs. That is the whole action item here — the design mechanics of impedance control are covered separately in Key Points of PCB Impedance Control Design, and PCB168's heavy copper page publishes ±10% impedance control as its stated figure.

Tighten locally, not globally

A global note reading "minimum line width 2mil" applies the tightest process condition to every square millimetre of every layer. The board does not need that, and the quote will reflect it.

The alternative costs you one drawing note:

```

Fine line requirement (HDI):

General routing, all signal layers .... 3mil / 3mil

BGA escape U12 (see area on fab dwg) .. 2mil / 2mil, L3 and L10 only

Finished copper, L3 / L10 ............. as per stackup, confirm before tooling

Acceptance ............................ measured line width report, fine line layers

```

Four lines. They replace a conditional quote with a firm one, and they give the CAM engineer something to check the stackup against instead of something to interpret.

Three things to read in the supplier's reply

When quotes come back, the fine line answer is usually one sentence buried in the middle. Read it for three things:

Does it commit per layer, or globally? A reply that repeats your tightest number without reference to layers has not engaged with the request. A reply that says "3/3mil confirmed on all signal layers, 2/2mil confirmed on L3/L10 escape region" has.

Is it conditional, and on what? Conditions are not a bad sign — they are how a competent supplier tells you which variable is still open. What matters is whether the condition is specific ("subject to confirmation of finished copper on L3") or open-ended ("subject to engineering review"). The first is a question you can answer today. The second is an unpriced risk.

Does it ask for the stackup? A fine line HDI supplier that confirms 2mil without asking to see your stackup has either seen enough similar work to be confident or is not checking. You cannot tell which from the quote, so ask. PCB168 validates line width, spacing and impedance against the stackup before production for exactly this reason.

What can be fixed at quote stage and what must go to engineering review

The pattern: anything inside a published range can be priced; anything at the edge of a published range needs your stackup in front of an engineer. That is not evasion, it is the only honest way to answer a question whose answer depends on inputs you have not sent yet.

Putting it together: a fine line HDI RFQ block you can paste

```

HDI FINE LINE REQUIREMENT

1. Line width / spacing

- General signal layers: ___ mil / ___ mil

- Tightest region: ___ mil / ___ mil

- Tightest layers: L__, L__

- Tightest region ID: ______________ (ref des / area on fab drawing)

1. Finished copper weight, per fine line layer

- L__: ___ L__: ___ (mixed weights? list all)

1. Acceptable finished line width deviation

- [ ] stated tolerance: ______

- [ ] governed by impedance tolerance instead: ______

- [ ] acceptance class per applicable IPC specification (named)

1. Verification and acceptance

- [ ] AOI to stated class [ ] measured line width report

- [ ] impedance verification [ ] first-article review before balance of lot

1. Attached

- [ ] stackup [ ] Gerber/ODB++ [ ] fabrication drawing with notes

- [ ] confirmation that stackup and fab notes agree on copper weight

```

Item 5's last checkbox catches a failure that has nothing to do with etching and everything to do with paperwork: a stackup and a fabrication note that disagree about copper weight. When they conflict, someone has to decide which one wins, and that decision should not be made silently at CAM. The mechanics of resolving that class of conflict are covered in PCB Fabrication Notes Checklist for Conflicting Files.

Once the block above is filled in, send it with the files through the quote request. If you are still deciding how much of the geometry to tighten, HDI PCB Cost Drivers: Where Quotes Differ and What You Can Relax covers which levers move price most, and HDI PCB Manufacturing Process explains where in the sequence fine line geometry gets locked in.

FAQ

Can I just write "2mil minimum" and let the supplier figure it out?

You can, and you will get a quote. It will be priced against the supplier's worst-case interpretation of your design, or against a friendly assumption that gets revisited after tooling. Neither is comparable to another supplier's number. The five inputs above take about ten minutes to fill in and remove that ambiguity.

Is 2mil/2mil a standard delivery specification at PCB168?

No. The HDI capability page lists 2mil/2mil as the *minimum* line width/space and 3/3mil as a key process feature. Treat 3/3mil as the practical fine line default and 2mil/2mil as a design-specific request requiring engineering confirmation against your stackup and copper weights.

Why does finished copper weight matter so much for a line width question?

Because etching removes copper sideways as well as downwards. Heavier copper means more lateral removal to compensate and more sidewall variation to control, so the achievable line width window narrows. This is directional and reliable; the specific compensation is process data confirmed against your stackup, not a published constant.

Should I specify line width tolerance or impedance tolerance on fine line pairs?

Pick one as governing and say so. If the pairs are controlled-impedance structures, impedance is usually the more meaningful acceptance criterion, since it is what the circuit cares about. Specifying both independently and tightly can create a contradiction the supplier has to resolve on your behalf.

Can one board carry both 2mil HDI routing and heavy copper current paths?

That combination needs a feasibility conversation before the RFQ, not a line item inside it. The two requirements pull the process in opposite directions — the heavy copper page's 6mil minimum line width against copper weights of 3oz and up shows why. Send the stackup, the current requirement and the fine line region, and ask for a construction recommendation rather than a price.

How do I check whether a supplier is actually reading my stackup?

Look at whether the quote's fine line commitment references your layers and copper weights, and whether it asks for anything. A per-layer answer with a specific open condition indicates the file was opened. A restatement of your own number with a generic caveat does not.

Related links

• Compact green HDI board with fine-pitch IC packages and a gold-plated dual-row pin header, the component density that drives fine line etching requirements
• HDI PCB capability page