Cheap HDI PCB Quote: Which Build Did the Supplier Assume?
Why an HDI quote drifts more than a standard multilayer quote
On a conventional multilayer board, most of the cost sits in things your files already state: layer count, outline, copper weight, finish, thickness. There is not much room for interpretation.
HDI is different because the same schematic and the same layout can be produced through structurally different routes. PCB168's published HDI range on the capabilities page is 1+N+1 to 4+N+4, with microvia ≥0.075mm and registration ±25µm. That range is not a list of equivalent options. Each step up the ladder adds sequential build-up work, meaning the panel goes through another full round of the shop: another lamination, another drill pass, another plating and imaging cycle.
The photo above is what that looks like physically. Bare copper panels sitting on a conveyor in a wet process unit. The board on the left and the board on the right may be for the same customer, and the difference between them may be nothing more than how many times each one comes back to this line. A single unstated line in your RFQ decides that.
Consequence: the gap between a cheap HDI quote and an expensive one is frequently a difference in process passes, not a difference in margin. Which means the gap will reappear later as a DFM query, a change request, or a board that works but does not match your intent.
The seven fields where an HDI quote can legally drift
Each field below has the same shape: what the supplier can assume, what it saves them, and how to detect it in a quote you already hold.
1. HDI level and lamination cycles
The assumption: your design needs a 2+N+2 route, but the quote was built as 1+N+1 with a through-via fallback for the connections that no longer reach.
Why it is cheap: each additional HDI level is another sequential lamination and its own drill/plate/image cycle. Dropping one level removes a full pass across the shop.
How to detect it: the quote states a layer count but no build notation. "10 layers HDI" is not a build. 1+8+1 is a build. If the number of layers is stated and the notation is not, the notation was assumed.
Lock it: *"Quote to build notation ___ (1+N+1 / 2+N+2 / 3+N+3 / 4+N+4) and state the number of sequential lamination cycles in your quote. If you propose a different notation, quote it as a separate line with the structural change described."*
Depth on the declaration itself: layer count and lamination cycle declaration.
2. Stacked vs staggered microvias
The assumption: your stack implies stacked microvias; the quote assumes staggered.
Why it is cheap: stacked microvias require the lower via to be filled and planarised well enough to land the next one on top, with registration held across levels. Staggering moves the upper via sideways onto fresh copper and relaxes that requirement.
How to detect it: the quote is silent on via structure, or says "microvia" with no stack/stagger word. Also watch for a quote that accepts your stack without a single registration comment — with registration published at ±25µm, a supplier reading a stacked structure usually has something to say about it.
Lock it: *"Microvia structure is ___ (stacked / staggered / mixed per layer pair). Confirm you are quoting this structure as drawn. If you require a change for manufacturability, identify the layer pairs affected before quoting."*
Depth: stacked vs staggered microvia declaration.
3. Microvia span and what the laser is expected to reach
The assumption: each microvia spans one dielectric layer. If your design expects a via to reach deeper, the quote may assume it gets split into two hops, or gets replaced by a mechanically drilled via.
Why it is cheap: single-span microvias are the routine case. Anything else changes the drill program, the aspect ratio the plating has to fill, and sometimes the level count.
How to detect it: you specified a via reaching from L1 to L3 and nothing in the response acknowledges it. The published capability set lists two drill routes — 0.1mm mechanical and 0.075mm laser — and they are not interchangeable at the same diameter. A quote that never says which route it used has chosen one for you.
Lock it: *"State the span of every microvia type in the stack (e.g. L1–L2, L2–L3) and whether it is laser or mechanically formed. Do not substitute a mechanical via for a laser via without written approval."*
4. Via-in-pad: filled and capped, or just filled
The assumption: your BGA area needs via-in-pad, filled and capped with plated copper so the pad is flat and solderable. The quote assumes resin fill without capping, or plugging only.
Why it is cheap: capping adds a plating step and a planarity requirement on top of the fill. Skipping it is invisible on a quote line and very visible at assembly.
How to detect it: the quote says "via in pad: yes." That answers whether vias sit in pads, not how they are closed. The capabilities page states Via-in-Pad filled and capped as the capability; a quote that only says "filled" has narrowed it.
Lock it: *"Via-in-pad treatment is ___ (resin filled and copper capped / filled only / plugged). Pad surface must be suitable for ___ assembly process. Confirm the treatment quoted, per area of the board if it differs."*
5. Line width and space: extreme grade or one notch back
The assumption: your densest area needs the finest available geometry; the quote assumes a relaxed grade because most of the board is relaxed.
Why it is cheap: yield and inspection burden rise sharply at the finest grade, and the whole panel is priced for its hardest feature. Quoting one notch back changes the price of the entire order. PCB168 publishes 2mil/2mil minimum line width and space on both the capabilities page and the HDI product page — but *capable of 2mil* and *priced at 2mil* are different statements.
How to detect it: compare the minimum trace/space in your own design rules against what the quote states. If the quote states nothing, it priced whatever its default grade is. A large price gap between suppliers with no other visible difference very often lands here.
Lock it: *"Minimum line width / space in the design is ___ / ___ , located in ___ . Quote to this grade. If you are quoting a relaxed grade, say so explicitly and quote the as-designed grade as an alternate."*
Related, from the fabrication side: fine line etching RFQ inputs.
6. Base material: FR-4 vs BT vs ABF
The assumption: you named a performance requirement; the quote assumes standard FR-4 because you did not name a material class.
Why it is cheap: the HDI product page lists FR-4 / BT / ABF as the HDI material set. These are not price-equivalent, and they do not behave the same through sequential lamination. FR-4 is the default a quote lands on when the field is blank.
How to detect it: the quote names no material, or names "FR-4" while your requirement was written as a thermal or electrical target rather than a material. Also check Tg: a Tg grade is part of the material decision, not a detail.
Lock it: *"Base material class is ___ (FR-4 / BT / ABF), Tg grade ___ . Substitutions require written approval before production. If you propose an alternative, state the class and why."*
Depth: FR-4 vs BT vs ABF base material declaration.
7. Impedance control and whether it is actually verified
The assumption: you asked for controlled impedance; the quote assumes calculated-and-built, with no measurement.
Why it is cheap: verification is work. The capabilities page publishes impedance control at ±5% (TDR verified) and lists TDR coupon in the QC set. A quote can say "impedance controlled" and deliver a stackup that was modelled but never measured, and nothing in the wording was false.
How to detect it: the quote says impedance controlled but mentions no tolerance, no coupon, and no report. Tolerance without a verification method is a calculation, not a result.
Lock it: *"Controlled impedance ___ ohm ±___ %, verified by TDR coupon, report supplied with shipment. Coupon to be included on the panel."*
Reading the low quote you already have
You do not need to reissue the RFQ to test this. Take the outlier quote and mark each of the seven fields as stated or silent.
- Mostly stated, and the statements match your design. The price difference is real. It may be capacity, panel fit, or commercial appetite. Proceed, and keep the stated fields as contract terms.
- Several silent fields. The price describes an unknown build. It is not comparable to the other three quotes yet, and averaging it into your budget will mislead you.
- Silent fields plus no engineering questions at all. Treat this as the strongest signal on the page. A dense HDI package that generates zero queries usually means the reviewer resolved every ambiguity internally rather than asking you. Those resolutions are the cheap build.
Then send one message, not a new RFQ: the seven lock sentences, asking for a restated quote against them. What comes back is a comparable number. Suppliers who cannot restate their price against stated build fields have told you something useful too.
The point of the exercise: you are not trying to disqualify the cheap supplier. You are trying to make all four quotes describe the same board so the cheapest one means something.
What to include so this does not recur
The seven fields above are the recurring gaps. Stating them up front is cheaper than reconciling quotes afterwards. The minimum build block in an HDI RFQ:
- Build notation and number of sequential lamination cycles
- Microvia structure (stacked / staggered / mixed) and the span of each via type
- Laser vs mechanical formation per via type
- Via-in-pad treatment and the required pad condition
- Minimum line width / space and where it occurs
- Base material class and Tg grade, plus a no-substitution clause
- Impedance value, tolerance, verification method and deliverable
Package-level completeness — Gerber, drill, stackup drawing, IPC class, test requirements — is covered separately in the HDI quote package checklist. Cost structure from the supplier's side is in HDI cost drivers and quote optimization. If you are still deciding whether the design needs HDI at all, start at HDI or conventional multilayer.
Current HDI capability values are published on the HDI product page and the capabilities page. Anything conditional — whether a specific stack is producible at a specific thickness, whether a span can be formed at a given diameter — needs engineering confirmation against your files rather than a published range. Submit files through the quote request form.
FAQ
Is a cheap HDI quote automatically a red flag?
No. It is an unresolved question. A low price with all build fields stated and matching your design is a real price. A low price with silent build fields is not yet a price for your board.
Can a supplier change the build without telling me?
If your package left the field open, they are not changing anything — they are filling a blank. That is why the fix is wording in the RFQ and PO rather than a complaint afterwards. Once a build field is stated and accepted, a change needs approval.
Which of the seven fields moves the price most?
It depends on the design, so no general ranking holds. Structurally, the fields that add or remove a full process pass — HDI level, microvia structure, via-in-pad capping — tend to move more than a field that only changes a material line. For your specific stack, ask each supplier which field they would relax first if you needed a lower number; the answers are informative.
Our quote says "HDI, 10 layers." Is that enough?
No. Layer count does not determine build. A 10-layer board can be built as 1+8+1 or 2+6+2, and those are different amounts of work. Ask for the notation and the lamination cycle count.
Can I just ask for the highest capability on everything?
You can, and you will pay for features you do not need, because the panel is priced for its hardest feature. The goal is an accurate build statement, not a maximal one. State the fine geometry where it actually occurs and let the rest of the board sit at a normal grade.
Do I need to compare stackup drawings from each supplier?
It is the most direct check. If each supplier returns a proposed stackup with layer sequence, dielectric thicknesses, copper weights and via spans, differences in build become visible without any price analysis. Suppliers who will not provide one before PO are asking you to compare prices without knowing what is priced.
Sources: PCB168 published capability pages capabilities and HDI PCB; existing PCB168 HDI declaration and quoting articles linked above. No unpublished PCB168 yield, lead-time, pricing, MOQ, capacity, equipment or customer-case data is used in this article.
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