HDI PCB Microvia Reliability Tests: What to Specify in the PO

Why a clean microsection is not a reliability result

A microsection shows the via at one moment, at room temperature, in the one or two places that were cut. Stacked and staggered microvias usually fail somewhere else: at the interface between the plated via and the target pad below it, or at the copper fill. That interface can look sound in a section and still separate when the board heats up during reflow.

The awkward part is that such a failure may be intermittent. The joint opens when the board is hot and closes again when it cools. A room-temperature continuity test on the finished board then passes, and the defect shows up later in your assembly line or in the field.

This is why HDI buyers increasingly ask for stress testing, not only a section report. The point of the PO language below is to make that request specific enough that two suppliers would run the same test and you could compare the answers.

Four things need to be stated:

• Which stress the board or coupon goes through
• What is tested: a coupon, a finished board, or both
• What counts as a pass
• How often the test is run

The three stress tests buyers usually mean

Reflow simulation (preconditioning). The coupon passes through repeated reflow-like heating to imitate assembly, with resistance of a via daisy chain monitored or measured before and after. IPC-TM-650 method 2.6.27 describes a convection reflow assembly simulation. For HDI with stacked microvias, this is often the most relevant test because it reproduces the exposure that triggers interface separation.

Thermal shock or thermal cycling. The coupon moves between a cold and a hot temperature for a set number of cycles, with continuity checked during or after. IPC-TM-650 method 2.6.7.2 covers thermal shock, thermal cycle and continuity. This targets fatigue over the product's life rather than the assembly step.

Interconnect stress test (IST). A DC current heats the coupon's own via chain, then it cools, and the cycle repeats while resistance is logged. IPC-TM-650 method 2.6.26 describes this DC current-induced thermal cycling. It is fast and gives resistance-versus-cycle data, but it needs coupons designed for the specific test system.

These tests answer different questions. Reflow simulation asks whether the vias survive assembly. Thermal cycling and IST ask how long they last afterwards. A PO that says "reliability test per IPC" without naming the method leaves the supplier to choose, and the cheapest choice may not cover the failure you are worried about.

Coupon or finished board

Stress tests are normally run on coupons rather than on product boards. A coupon is a small test structure built on the same panel as your boards, so it shares the same lamination, drilling and plating. It also carries a daisy chain of vias long enough to make a resistance change measurable.

That only works if the coupon actually represents your design. Three points to settle in the PO:

• Structure match. The coupon should contain the same microvia structure as the product: same stack (for example 1+N+1 or 2+N+2), stacked or staggered, filled or unfilled, and the same capture and target pad sizes. A coupon with single-level microvias says little about a board with three stacked levels.
• Who designs it. Either you supply the coupon design, or the supplier adds its standard coupon and shows you how it maps to your structures. Write down which. IPC-2221 and IPC-6012 / IPC-6016 describe coupon concepts by name; IST coupons follow the test-system vendor's design rules.
• Where it sits. State that coupons are placed on the production panel, not on a separate test panel. A separate panel can be processed under different conditions.

Testing finished boards is possible but limited. You can precondition product boards through reflow simulation and then section them, but you cannot easily monitor resistance across a long via chain on a real product. Many buyers use coupons for the stress data and finished-board sections only to confirm the failure location.

What counts as a pass

A pass criterion has two parts: an electrical threshold and a physical confirmation.

Electrical. Resistance of the daisy chain is measured before stress and then during or after. The criterion is a maximum resistance change, usually expressed as a percentage of the starting value, over a stated number of cycles. The actual percentage and cycle count depend on your product and on the industry spec you follow. They should be written by you or agreed in writing, not chosen by the supplier after the test.

Physical. When a chain fails, or at the end of a qualification run, the coupon is sectioned to find where the failure happened. Typical findings are separation at the target pad, cracks in the via barrel or fill, or problems in the inner-layer connection. The section turns "the resistance went up" into "this interface is the weak point", which is what you need to decide whether to accept a corrective action.

Also state what happens to a failed result. A common approach is: a single failing coupon triggers sectioning and a supplier analysis, and the lot is held until you decide. Without this, a failing coupon may simply be retested until one passes.

When the test is run

Frequency drives cost, so it is worth being explicit:

Lot-level testing is the expensive part. If you do not need it for every lot, say so, and specify instead that coupons from every lot are retained for a stated period so you can test them later if a problem appears.

PO wording you can adapt

The text below is a starting point for your own quality agreement. It is not legal advice and not PCB168 standard terms. Replace each [N] with a value you have chosen or agreed.

> Microvia reliability. For part number [P/N], the supplier shall place reliability coupons representing the product's microvia structures (stack-up, stacked/staggered arrangement, fill type and pad sizes) on each production panel.

>

> Qualification. Before first shipment, coupons from [N] panels shall be tested by [reflow simulation per IPC-TM-650 2.6.27 / thermal cycling per IPC-TM-650 2.6.7.2 / IST per IPC-TM-650 2.6.26] for [N] cycles. Pass: daisy-chain resistance change no greater than [N] %. Failed or end-of-test coupons shall be microsectioned and the failure location reported.

>

> Requalification. Qualification shall be repeated after any change of laminate, plating or via-fill process, laser drilling source, or manufacturing site.

>

> Lot control. [Test per lot / retain coupons from every lot for [N] months for buyer-requested testing.]

>

> Nonconformance. A failing coupon places the lot on hold pending buyer disposition. Retesting of replacement coupons does not release the lot without buyer approval.

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> Reporting. Reports shall state test method, coupon ID, panel and lot traceability, cycle count, resistance data and section images.

Two things make this clause work in practice. First, it names a method instead of "reliability testing". Second, it ties requalification to the process changes most likely to affect microvias. That second point should match the change-notification terms in your supply agreement, so a notified change automatically triggers the retest.

How this fits with the rest of your HDI package

Reliability testing sits on top of decisions you have already made in the RFQ:

• The microvia structure itself, which you declare in a stacked or staggered microvia declaration.
• Whether vias are in pads and filled, covered in via-in-pad filled and capped requirements.
• Electrical test and the separate coupons used for it, covered in netlist and coupon declarations for HDI electrical test.

Electrical test confirms that nets are connected and isolated at room temperature. Reliability testing confirms that the connection holds under heat. Keep them as separate lines in the PO so neither is assumed to cover the other.

If you are still choosing a build, the HDI PCB product page and the capabilities overview describe the structures PCB168 discusses with buyers. When your test plan is ready, include it with your files through the quote request so it is priced from the start rather than added after award.

Checklist before you send the PO

• Test method named by IPC-TM-650 number, not "per IPC"
• Coupon structure matches the product's microvia stack
• Coupon designer and placement on the production panel agreed
• Resistance-change threshold and cycle count written as numbers you chose
• Sectioning required on failure, with location reported
• Requalification triggers listed
• Lot policy chosen: test each lot or retain coupons
• Hold and disposition rule for failing coupons
• Report content and traceability fields defined

FAQ

Is a microsection report enough to prove microvia reliability?

No. A section shows the via at room temperature in the places that were cut. Interface separation in stacked microvias often appears only under heat, so a stress test with resistance monitoring is needed to show the via survives.

Which test should I ask for first?

For stacked microvias that will go through lead-free assembly, reflow simulation is usually the most relevant starting point because it reproduces the assembly exposure. Add thermal cycling or IST if your product needs life data or you want to compare suppliers.

Can the supplier choose the coupon design?

Yes, if you agree to it in writing and the coupon matches your microvia structure. Ask the supplier to show which coupon structure represents which product via.

Who sets the pass threshold?

You, or both parties in writing before testing. The threshold should come from your product requirements or the industry specification you follow, not from the test result.

Do I need to test every lot?

Not always. Many buyers qualify fully once, repeat after process changes, and retain coupons from each lot so they can test later if needed. Lot testing adds cost and should be a deliberate choice.

What happens if a coupon fails?

State it in the PO: the lot is held, the coupon is sectioned, the supplier reports the failure location and cause, and you decide on disposition. Retesting other coupons should not release the lot automatically.