HDI PCB Electrical Test: What "100% Tested" Leaves Out of Your RFQ

"100% electrical test" is a verb, not a clause

Almost every HDI RFQ carries the line. Almost none of them say what it binds.

Read it as a supplier would. *Electrical test* means the boards will be checked for continuity and isolation before shipment. *100%* means every board, not a sample. That is the whole content of the sentence. It does not identify which netlist the boards were compared against. It does not say which structures were reached by the test. It does not state the criteria under which a net was called open or shorted. It does not say whether coupons were tested, retained, or discarded. And it does not promise you a single sheet of paper afterwards.

Every one of those gaps is a place where two suppliers can quote the same line, perform entirely different work, and both be telling the truth.

This matters more on HDI than on a conventional multilayer board, for one structural reason: most of what you are buying on an HDI board is not reachable by a probe. Stacked and staggered microvias, buried vias, the copper-to-copper interface at each lamination cycle — these sit inside the stack. A continuity test confirms that the net, as a whole, conducts right now. It does not distinguish a robust microvia interface from a marginal one that conducts today and separates in the fourth reflow cycle. On a two-layer board, "continuity passed" and "the interconnect is sound" are nearly the same statement. On a 10-layer, 3-stage HDI board, they are not.

So the question to settle in the RFQ is not *whether* the boards get tested. It is: what did the test actually prove, and what evidence of that comes back with the shipment?

Four declarations close the gap. None of them require you to know the supplier's equipment, and none of them are expensive to add. They are lines of text.

Declaration 1: which netlist, which revision, and who supplies it

A bare-board electrical test is a comparison. The board is measured against a reference, and the reference is a netlist. If the RFQ does not name the reference, the supplier picks one.

There are two ways a netlist arrives at a fab, and they carry different risk:

You supply it. You export an IPC-D-356 netlist (or ship an IPC-2581 package, which carries the netlist inside it) from the same design database revision that produced the fabrication data. The test then compares the board against *your* intent.

The fab extracts it. The fab derives a netlist from your Gerber data, then tests the board against that. This is routine, it is often the default, and it has one consequence worth understanding clearly: the test now proves the board matches the Gerbers. It cannot catch an error that already exists in the Gerbers. If a plane got stitched to the wrong net during output, an extracted-netlist test will pass every board and confirm the mistake on all of them.

Neither option is wrong. An extracted netlist is a legitimate manufacturing check and for many boards it is sufficient. But the two prove different things, and you should know which one you are buying.

What to write into the RFQ:

• Whether the test netlist is buyer-supplied or fab-extracted.
• If buyer-supplied: the format and the file name, plus the design revision it was exported from.
• A requirement that the netlist revision used at test be recorded and reported.
• A rule for mismatch: if the fab's extracted netlist disagrees with your supplied netlist, the boards stop and you get a query — rather than the fab silently picking the one that makes the boards pass.

That last line is the one buyers most often omit, and it is the one that catches real errors. A netlist discrepancy found before plating is a question. Found after shipment, it is an argument.

Declaration 2: test scope and structural coverage

The second gap is coverage. "Every board" and "every net" are not the same claim, and neither one tells you which *structures* participated.

Three things are worth separating in the RFQ:

Net coverage. Does the test cover all nets, or all nets with at least two accessible test points? Nets that terminate only under a BGA, inside a via-in-pad structure, or on a plane with no exposed access may not be fully reachable. A net can be partially tested — enough to confirm it is not shorted to its neighbour, not enough to confirm every branch is continuous.

Access points. On a fine-pitch HDI board, what the probe can touch is constrained by the pad geometry and by whether the vias are filled and capped. If your design relies on vias being probed, and the build fills and caps them, the access assumption changes. This is worth raising at RFQ stage because it interacts with a decision you have probably already made elsewhere in the build; PCB168 covers that decision in via-in-pad on HDI PCB: filled and capped are two different declarations.

Structures not covered by continuity at all. Interconnect integrity at the microvia interface, dielectric withstand between layers, and resistance change after thermal stress are not continuity findings. If you need any of them, they are separate requirements with separate methods, and they usually live on a coupon rather than on the board. That is Declaration 4.

A practical way to phrase the scope line: ask the supplier to state net coverage as a condition rather than a number. "All nets with two or more accessible test points, with any excluded nets listed by name in the test report" is enforceable without either party guessing. "100% tested" is not.

One related trap: a supplier quoting against a thinner interpretation of scope will quote lower, and the difference will not be visible in the price breakdown. If you are comparing HDI quotes that diverge and cannot see why, test scope is one of the places the difference hides. PCB168 covers the broader version of that comparison in HDI PCB cost drivers: where quotes differ and what you can relax.

Declaration 3: whose criteria, and written where

A test produces a verdict, and a verdict needs a threshold. Somewhere a value decides that this net is open and that one is continuous. The question for the RFQ is not what the value should be — that is the fab's process domain and depends on their equipment. The question is whose document it comes from and whether you ever see it.

Three positions are available:

1. Fab-standard criteria. The fab applies its own internal thresholds, derived from its equipment and its reading of the applicable industry standard for bare-board electrical test. Most orders run this way.
2. Standard-referenced criteria. The RFQ names the industry test standard and the class, and requires the fab to confirm it tests to it. IPC-9252 is the relevant standard family for bare-board electrical test requirements; IPC-6012 carries the performance class structure that most HDI purchase specifications already reference.
3. Buyer-specified criteria. You state the thresholds. Appropriate for qualified programmes, usually unnecessary otherwise, and it obliges you to defend numbers you may not have derived.

Position 2 is the sensible default for most HDI buying, and it costs nothing to write. What it buys you is not a tighter test — it is a *named* test. Once the standard and class are in the PO, "the boards passed" has a definition that both parties can look up, and a disputed batch has a document to argue from instead of two recollections.

Two cautions on wording. First, name the standard and the class, and stop there; do not transcribe threshold values into your PO from a standard you have not verified against the current revision. Second, if your purchase specification already declares a performance class for the board overall, make sure the test line references the same class rather than introducing a second one. A specification that contradicts itself is weaker than one that says less. PCB168 covers how the specification sheet itself gets bound to the quote in PCB fabrication specifications: writing a sheet that binds the quote.

Declaration 4: coupons — required, retained, and who they speak for

This is the declaration that separates an HDI order from a conventional one, and it is the one most often missing.

A test coupon is a small piece of copper and dielectric carried on the same production panel as your boards, built through the same process, and designed to be destroyed or stressed so that something can be measured which cannot be measured on a shippable board. For HDI, the structures of interest are the ones buried in the stack: the microvia interfaces, the layer-to-layer registration, the plating in high-aspect-ratio holes.

Coupons answer a different question from the board test. The board test asks *does this board conduct correctly today*. The coupon asks *is this build sound*. You can pass the first and fail the second, and that combination is exactly the failure mode that shows up weeks later as intermittent faults after assembly.

Four things need to be declared, and they are usually declared badly or not at all:

Required or not. Coupons occupy panel area and consume process time, so they are not free, and they are not automatic. If you want them, say so in the RFQ — not in a later email. The cost belongs in the quote you compare, otherwise you are comparing a quote with coupons against one without and reading the difference as efficiency.

Which coupon, for which structure. A coupon designed to reveal microvia interface quality is not the same artefact as one designed to verify dielectric spacing or impedance. Name the structure you want evidence about, and let the supplier propose the coupon design; this is more productive than specifying a coupon geometry you copied from another programme.

Who retains them, and for how long. Coupons that are tested and discarded give you a report. Coupons that are retained give you the ability to re-examine a specific lot later, when a field failure has forced the question. Retention is a terms question, not a technical one, and it needs a stated period.

Whose result governs. This is the clause that matters in a dispute. If the board-level electrical test passes and the coupon result is marginal, what happens to the shipment? Three answers are defensible — the coupon governs and the lot holds, the coupon is informational only and the lot ships, or the lot ships under a documented concession with your approval. Any of the three is workable. Having never decided is not. The default when nobody decided is that the boards ship, you receive a report you did not read, and the question reopens after assembly.

Note the boundary of this article: coupon-based evidence here is about the bare board. Once parts are on the board, the test and inspection questions change entirely — different methods, different criteria, different owner. PCB168 covers that side in defining PCBA test and inspection requirements before you get quoted.

What should come back with the shipment

Declarations one to four describe what gets done. This section is about what you can read afterwards, which is the part that determines whether any of it is enforceable.

A useful bare-board test record carries, at minimum:

• The netlist identity and revision the boards were compared against.
• The test standard and class applied.
• Net coverage as actually achieved, with excluded nets named rather than summarised.
• The quantity tested, the quantity passed, and the disposition of anything that failed.
• Panel or lot identification that ties the record to the boards in the box.
• Coupon results where coupons were required, identified to the same lot.

The last point is the one that silently breaks. A test report that cannot be matched to the physical batch in front of you is a document about boards in general. If the lot identification on the report does not correspond to a marking you can find on the delivered panels, you have paperwork but not evidence — and the whole chain built by the four declarations terminates in nothing. This is a document-package problem rather than a test problem, and it is worth settling in the same PO.

Two further things worth asking for, both cheap:

Failure disposition, not just failure count. "Two boards failed and were scrapped" closes the loop. "Yield was as expected" does not. If scrap handling and delivered quantity are not already settled in your PO, they interact with this directly; PCB168 covers that in HDI PCB manufacturing process: who absorbs scrap and who owns the delivered quantity.

Notification on retest. If a board failed, was reworked or re-tested, and then passed, you want that visible rather than averaged away.

Turning the four declarations into RFQ text

The four declarations are not a long addition. Written out, they fit in a short block that can sit directly under the electrical test line in your RFQ:

> Bare-board electrical test

> 1. Test netlist: [buyer-supplied, file and revision named] / [fab-extracted from fabrication data]. Netlist revision used at test to be recorded in the test report. Any discrepancy between extracted and supplied netlist to be raised as an engineering query before further processing.

> 2. Coverage: all nets with two or more accessible test points. Excluded nets to be listed by name in the test report.

> 3. Criteria: per [named bare-board electrical test standard], performance class per the class already stated in this specification. Supplier to confirm the standard and class applied.

> 4. Coupons: [required / not required]. Structure of interest: [microvia interconnect integrity / other]. Coupon design proposed by supplier for buyer approval. Retention period: [period]. Governing rule where coupon and board results diverge: [coupon governs and lot holds / informational only / ships under documented concession with buyer approval].

> 5. Deliverables with shipment: test report carrying netlist revision, standard and class, achieved coverage with excluded nets, quantity tested and passed, failure disposition, and lot identification traceable to markings on the delivered panels. Coupon results identified to the same lot where applicable.

Two notes on using it. First, bracketed items are decisions you make, not blanks for the supplier to fill. Leaving them open reproduces the problem the block was written to solve. Second, this is an RFQ block, so it has to survive into the PO. A requirement that shaped the quote but never entered the order has no standing at delivery, and this is the most common way the work above gets wasted.

If you are assembling the RFQ package from scratch rather than patching an existing one, this block sits inside a longer list of inputs. PCB168 covers the full package in HDI PCB quote package checklist: stackup, microvias and acceptance inputs, and the HDI capability context in HDI PCB manufacturing.

Supplier answers, and the follow-up each one needs

The four declarations tend to produce a predictable set of replies. Each has a useful second question.

"Yes, we do 100% electrical test on all boards." — Against which netlist, and is it one we supplied or one you extracted?

"We test to the applicable IPC standard." — Which standard, and which performance class? Please state both in the test report.

"Coverage is 100%." — Including nets with only one accessible test point? If any nets are excluded, can they be listed by name in the report?

"Coupons are included." — Which structure do they characterise, who retains them and for how long, and if a coupon result is marginal while the boards pass, does the lot ship?

"We'll send the test report." — Carrying the netlist revision, standard and class, achieved coverage, failure disposition, and a lot identifier that matches a marking on the panels?

"That's not something we usually declare." — A legitimate answer. The useful response is to ask what they *can* declare, and then decide whether that is enough for this programme. A supplier who states a narrower scope clearly is easier to work with than one who agrees to everything in writing and performs to their own default.

That last case is worth dwelling on. The purpose of these declarations is not to extract maximum commitment. It is to make the scope *visible* so that two quotes become comparable and a delivered batch has a definition to be measured against. A clearly stated narrow scope achieves that. An unexamined "100% tested" does not.

If you are running this exercise across more than one candidate supplier, the completeness of the answers is itself a signal, and it is more informative than price at this stage. PCB168 covers the surrounding evidence request in HDI PCB supplier qualification: capability evidence to request without a site visit.

FAQ

Is "100% electrical test" ever sufficient on its own?

For a simple board from a supplier you have an established history with, often yes. The line does real work: it commits to testing every board rather than a sample. It becomes insufficient when the board carries structures a continuity test cannot characterise — which is the normal condition on HDI — or when you are qualifying a new supplier and need the test to be defined rather than assumed.

If the fab extracts the netlist from my Gerbers, is the test worthless?

No. It is a genuine manufacturing check: it proves the board matches the data that was used to build it, which catches process faults such as opens from etch defects or shorts from lamination problems. What it cannot do is catch an error already present in your output data. If you want the test to verify intent rather than execution, supply the netlist from your design database.

Do I need coupons on every HDI order?

No, and requiring them everywhere wastes panel area and money. The useful trigger is change: a new build, a new supplier, a revised stackup, a move from prototype to production, or a programme where field failure cost is high. For a repeat order on a frozen build from a qualified supplier, the board test plus the established history usually carries it.

Who should own the coupon design?

Let the supplier propose it against the structure you named, then approve it. They know which coupon their process and measurement setup can meaningfully characterise. Specifying a coupon geometry borrowed from another programme tends to produce an artefact that is built as drawn and tells you less than intended.

What if the coupon result is marginal but every board passed?

That is precisely the case to decide in advance, which is why Declaration 4 includes a governing rule. Without one, the commercial default takes over: the boards ship. Deciding beforehand costs one sentence; deciding afterwards costs a negotiation with a built batch already in transit.

Does any of this change what I pay?

Requiring coupons has a real cost, because they occupy panel area and process time. The other three declarations are text, and they generally do not change the price — they change whether the price you were quoted covers the work you assumed. That is the more common source of surprise.

Can I add these declarations after the PO is placed?

You can ask, and a cooperative supplier may accommodate the reporting items. But coupons and netlist source affect how the panel is built and how the job is set up, so after certain points in the process they stop being additions and become a rebuild. Front-load them into the RFQ, where they are free.

来源

• 本文方法论基于公开行业标准体系的结构，仅按名引用：IPC-9252（裸板电测要求）、IPC-6012（刚性板性能规范与等级结构）、IPC-A-600（成品板可接受性）、IPC-D-356 与 IPC-2581（网表与数据交换格式）、IPC-TM-650（试验方法手册）。全文未复述任何条款编号下的具体数值，使用者应以所采用标准的当前版本为准。
• PCB168 能力口径以站内能力页公开内容为准，具体以工程评审确认；本文未声明任何 PCB168 自有设备、测试通道、判据数值、良率、交期或客户案例。
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