Heavy Copper PCB for Power Supply: Deriving Copper Weight From Current and Rise

Freeze four functional conditions before you talk about copper

Most heavy copper RFQs arrive with one number in them: a current. One number cannot produce a copper weight, because the same current at a 5% duty cycle in a 25°C cabinet and at 100% duty in a sealed 70°C enclosure are two different boards.

Fix these four first, in writing, and treat them as the input to everything below:

1. Current, split into peak and continuous. Peak with its duration and repetition rate; continuous as the RMS value the copper actually sees. If you only have one figure, say which one it is.
2. Duty cycle. Not a feeling — a percentage with a time base. A 200A pulse for 2ms every 500ms and 200A held for a minute are not comparable loads on copper.
3. Ambient at the board, not in the room. Inside an enclosure, next to a heatsink, downstream of a fan, or in still air. This is the number people substitute room temperature for, and it is usually the largest single error in the whole derivation.
4. Allowed temperature rise for the conductor. The delta you accept above that ambient. This is a design choice, not a physical constant, and it is the one condition that most directly converts into copper.

Notice what these four have in common: they are all yours. No supplier can supply them, and no copper weight is defensible without them. Every subsequent question — inner or outer layer, 4oz or 6oz, 1mm or 3mm wide — reduces to arithmetic on these four once they are frozen. Leave any of them open and you are asking a manufacturer to guess your operating conditions, which is how "we assumed continuous" ends up in a post-failure email.

Write them as four labelled lines, not prose. You will reuse them verbatim in the RFQ.

Peak versus continuous: how duty cycle changes the answer

Copper temperature is a thermal integration, not an instantaneous response. A trace has mass and it sits on a laminate that conducts heat away, so a short pulse dumps energy the copper can absorb and shed before it reaches steady state, while a sustained current pushes the conductor to whatever equilibrium its geometry and surroundings allow.

Practically, this splits your design into two regimes:

• Low duty cycle, short pulses. The limiting concern is often not steady-state rise but the cumulative heating of repeated pulses and the peak instantaneous current density at the narrowest point of the path. Sizing here from the peak current as if it were continuous will over-specify copper substantially.
• High duty cycle or continuous. Steady-state rise governs. Size from the RMS current, and treat the peak only as a check on the narrowest necks and via transitions.

Two places where duty cycle reasoning commonly goes wrong. First, people apply the duty cycle to the wrong quantity — heating scales with the square of current, so a 50% duty cycle does not halve the thermal load of a given peak. Second, the duty cycle at the connector is not the duty cycle at every point along the path; a shared return or a common plane section can be carrying the sum of several intermittent loads and be effectively continuous.

If your peak and continuous figures differ by more than a factor of two, state both in the RFQ and say which one the geometry was sized against. That single sentence prevents the most expensive category of misunderstanding on power boards, and it costs you nothing to write. Where the pulse behaviour is genuinely borderline, ask for engineering review rather than adding a safety factor in copper — reviews are free, extra copper weight is not.

Inner and outer layers do not get the same treatment

This is where a single copper callout stops working. On the PCB168 heavy copper page the copper weight range 3oz–20oz applies to a build, but two layers with the same nominal weight do not end up with the same finished copper or the same thermal behaviour.

• Outer layers receive electrolytic copper during plating. Finished copper on an outer layer is the starting foil plus what plating adds. They are also exposed to air on one side, which changes how heat leaves the conductor.
• Inner layers are not plated after lamination. Their finished copper is the foil minus etch loss, and they are buried in dielectric with laminate on both faces.

Two consequences for your derivation. First, an inner-layer conductor and an outer-layer conductor at the same nominal weight and width are not interchangeable in a thermal budget — the layer position belongs in your specification alongside the weight. Second, on a multilayer power board you almost certainly want a mixed-weight build rather than a uniform one. The published PCB168 approach for multilayer heavy copper pairs thin 1–2oz signal layers with 3oz–20oz power layers in the same stackup, so control and sense routing does not inherit the spacing penalties of the power planes.

So the deliverable from this step is not "6oz". It is a per-layer table: which layers carry power, at what weight, and which layers carry signals. That table also answers a question the supplier would otherwise ask you, which shortens the quote cycle.

For how copper weight interacts with layer count and finished board thickness — three published ranges that constrain each other rather than three independent dials — see our thick copper multilayer layer count guide.

How to use the two published starting points, and how not to

The PCB168 heavy copper page publishes two concrete anchors. Both are useful, and both are explicitly labelled as starting points on that page. Quoted with their original qualifiers:

• A 4oz (140µm) inner layer typically needs ~0.35mm trace width per 10A at a 10°C rise.
• A 6oz (210µm) external trace around 2.5–3mm wide can sustain tens of amps at a modest temperature rise, though the exact width depends on your allowed rise, ambient and layer position.

Use them for three things. As a sanity check: if your own calculation lands an order of magnitude away from these, you have an error in units, layer assumption or ambient. As a scaling anchor: they tell you roughly what a decade of current costs you in width at each weight, which is enough to choose between weights before detailed layout. As shared vocabulary: citing the same anchor the manufacturer publishes means your RFQ and their review start from one reference.

Do not use them for these. They are not a load table — the 0.35mm figure is stated per 10A at a specific 10°C rise on an inner layer, and moving any of those three conditions changes it. They do not transfer between layer positions, because the inner figure and the outer figure describe different thermal environments. And they are not a substitute for the four frozen conditions: both anchors are conditional, so applying them without stating your ambient and allowed rise reproduces exactly the ambiguity they were meant to remove.

One more constraint worth being explicit about: do not ask a supplier to recite current-carrying tables from the standards, and be wary of any that hands you a universal number. Cite IPC-2221 by name for conductor sizing intent and let the geometry be reviewed against your stated conditions. Naming the standard is enough; a number lifted out of its conditions is not evidence of anything.

What a 6mil minimum line width leaves you for control signals

The heavy copper page publishes a 6mil minimum line width. On a power-only board that number rarely matters, because your power geometry is measured in millimetres. On a mixed board it becomes the constraint that decides whether your control and sense routing fits.

Read it as a floor, not a target. Two reasons to stay above it on a heavy copper build. Thick copper etches with sidewall taper, so the narrowest features are the ones most affected by whatever compensation is applied — a trace designed at the floor has no margin left if compensation shifts it. And spacing, not just width, grows with copper weight; a fine trace routed between two heavy planes may clear on width and fail on the gap.

Which is the practical argument for the mixed-weight stackup from the previous step: put the signals on thin layers where the 6mil floor is comfortable, and keep the heavy weights on the layers that need them. If your design forces fine geometry onto a heavy copper layer, that is the specific item to flag for engineering review before RFQ, because it is a feasibility question rather than a pricing one.

If impedance matters on those signal layers, the same page publishes impedance control ±10%. Treat controlled-impedance nets on a mixed-weight board as a stackup constraint to be reviewed with the copper weights, not as something to resolve after the copper is fixed. Our multilayer stackup guide covers how layer assignment and dielectric choices interact once both requirements are on the table.

Temperature rise is a budget, and the board is only part of it

The allowed rise you froze in step 1 is not spent entirely on the conductor. It is a budget shared across a chain: conductor to laminate, laminate through the stackup, board surface to whatever removes the heat, and the ambient you assumed. Copper weight only buys you the first term.

Three interfaces that change how much copper you actually need:

• What the board is mounted to. A power plane bolted to a chassis or coupled to a heatsink loses heat by a path that has nothing to do with copper weight. Add that path and the same current may fit on less copper.
• Adjacent copper. Heavy planes on neighbouring layers spread heat laterally. This is why a per-layer table beats a single number: the thermal answer depends on what is above and below.
• Base material. The page publishes FR-4 TG170/TG180 for heavy copper builds. High-Tg laminate is about surviving sustained thermal load and lamination stress, not about conducting heat better than standard FR-4. Do not spend part of your thermal budget on an improvement the material does not provide.

The failure mode worth naming: designers who cannot get the rise they want often respond by adding copper weight, when the constraint is that the heat has nowhere to go. More copper spreads heat more evenly inside a sealed volume; it does not remove it. If your derivation keeps demanding more weight, check the exit path before you change the callout. Our PCB thermal management notes cover the board-level side of that path.

Where the rise budget depends on a mounting or airflow assumption you cannot yet confirm, write the assumption into the RFQ as an assumption. A stated assumption gets reviewed. An unstated one gets defaulted.

The four lines that belong in your RFQ

Everything above collapses into four lines. Put them in the RFQ body, not in an attachment, and keep them this short:

1. Electrical load. Peak current with duration and repetition rate; continuous RMS current. State which one the geometry was sized against.
2. Thermal conditions. Ambient at the board, allowed conductor temperature rise, and the mounting or airflow assumption behind it.
3. Per-layer copper weight, as finished copper, with layer position. For example: power layers at a stated weight, signal layers at a stated weight, and whether the numbers are base or finished. Say finished, and say it explicitly.
4. Critical geometry with its condition. The width of the narrowest power conductor and the narrowest signal trace, each with the layer it sits on, plus a note that widths were derived at the stated rise and ambient and are open to a manufacturability review.

That fourth clause matters more than it looks. It tells the manufacturer your widths are engineering outputs rather than arbitrary constraints, which is what allows them to propose a better geometry instead of quoting something they know is awkward. It converts the RFQ from a set of demands into a reviewable design intent, and reviewable intent is what gets you a comparable quote.

Two things to leave out. Do not specify a copper weight without stating whether it is base or finished — that is the single most common heavy copper dispute, and it is a definition gap, not a technical one. And do not add a blanket safety factor on top of a derivation you already did conservatively; you will pay for it in spacing, board thickness and etch difficulty.

When the four lines are ready, PCB168 publishes the ranges you are quoting into: 3oz–20oz copper weight, 1–16 layers, 0.8–6.0mm board thickness, 6mil minimum line width, HASL/ENIG/OSP finishes, FR-4 TG170/TG180 base material and ±10% impedance control, with online quoting from Gerber files and prototypes typically shipping in 3–5 working days. Start from the heavy copper PCB page to confirm your combination sits inside those ranges, then send the four lines through instant quote or ask for a manufacturability review via contact. If your power board also needs assembly, PCB assembly is where the thermal profile question for heavy copper joins the conversation.

FAQ

Is 4oz or 6oz right for a power supply board?

Neither answer exists without your four conditions. The published anchors give you the shape of the tradeoff: a 4oz (140µm) inner layer typically needs ~0.35mm per 10A at a 10°C rise, and a 6oz (210µm) external trace around 2.5–3mm wide can sustain tens of amps at a modest rise, though the exact width depends on your allowed rise, ambient and layer position. If your derivation says 4oz fits with margin at your stated ambient, 6oz buys you width you did not need and spacing penalties you did.

Can I just specify the heaviest copper available to be safe?

You can specify up to 20oz, but "safe" is the wrong frame. Heavier copper widens required spacing, drives board thickness, complicates etching and drilling, and can push your fine signal geometry below what is comfortable against the 6mil minimum line width. Over-specified copper is a real cost and sometimes a feasibility problem, not a free margin.

Should I quote base copper or finished copper?

Quote finished copper, state it explicitly, and state it per layer with layer position. Outer layers gain electrolytic copper during plating while inner layers finish at foil minus etch loss, so a single nominal weight is at least two different finished numbers on the same board. Leaving this implicit is the most common source of a heavy copper acceptance dispute.

How do I handle a large gap between peak and continuous current?

State both, with the peak's duration and repetition rate, and say which one the geometry was sized against. Heating scales with the square of current, so a duty cycle does not scale the thermal load proportionally. If the pulse behaviour is borderline, ask for engineering review rather than covering it with extra copper weight.

What ambient temperature should I use?

The temperature at the board in its enclosure under load, not room temperature. Substituting room ambient is the largest single error we see in these derivations, because it silently consumes the entire rise budget before the copper does any work.

Does high-Tg FR-4 reduce my temperature rise?

No. FR-4 TG170/TG180 is published for heavy copper builds because it withstands sustained thermal load and lamination stress, not because it conducts heat better than standard FR-4. Budget your rise on the basis of conduction paths and the exit path to ambient, and treat high-Tg as reliability rather than thermal performance.

Can power and signal layers share one heavy copper board?

Yes, and on most power boards they should. The published multilayer approach pairs thin 1–2oz signal layers with 3oz–20oz power layers in one stackup, which keeps control and sense routing away from the spacing penalties of the heavy layers. Submit a per-layer weight table rather than a single copper callout.

What if my calculated width does not fit the available board area?

That is a stackup question, not a copper weight question. Options include splitting current across parallel layers, moving a conductor to an outer layer where the thermal environment differs, or revisiting the rise budget and the heat exit path. All three need a manufacturability review with your four conditions attached; changing the copper callout alone will not resolve it.

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