HDI PCB for Tablets vs Wearables: Build Selection and RFQ Inputs | PCB168

Send an RFQ for an HDI board and there is a good chance the first thing back is not a price. It is a request: outline, target finished thickness, minimum BGA pitch, stackup intent - we need a feasibility review first.

That reply is not a stall. It is telling you something structural about HDI purchasing: HDI is not a part number you can select, it is a set of consequences your end device decides. And the part buyers most often miss is that different devices push those consequences in opposite directions.

Wearables and tablets are the clearest example of that. Both appear on the PCB168 HDI application list (smartphones, tablets, wearable devices, digital cameras, laptops, automotive electronics), so they look like one requirement. They are not. Their first constraint lives on a different axis entirely:

• Wearables: area and thickness are locked by the enclosure before the circuit exists. The board has to fit a volume it did not get to negotiate.
• Tablets: area is comparatively generous and thickness is not watch-extreme. What is tight is part density, layer count, and registration across a large panel.

Those two sentences decide what you send first. Below they are handled separately, then merged into one input sheet.

Scope, so this stays useful: this article assumes you have already decided on HDI - if that is still open, start with HDI or conventional multilayer: the RFQ decision. Build selection for 5G modules, handsets and automotive is covered separately and not repeated here: HDI build selection for 5G modules, handsets and automotive.

1. What "build-up level" actually counts: process rounds, not product tiers

The PCB168 HDI page gives a stackup range of 1+N+1 to 4+N+4. Read it in three parts: the outer numbers are how many HDI build-up layers sit on each side, and N is the core, a conventional multilayer structure. So 1+N+1 is one build-up layer per side, 4+N+4 is four.

The number itself matters less than what it counts. Each additional build-up level means another round of laser drilling, plating and lamination. Build-up level is a count of process rounds - it maps directly onto cycle time and process risk, not onto a quality grade. The relationship between layer count and lamination cycles is covered in HDI layer count and lamination cycles in the RFQ and not recalculated here.

Which gives one purchasing rule: build-up level should be the minimum your requirement forces, not the maximum your budget allows. What forces that minimum is your end-device data.

2. Wearables: lock outline and thickness, then let build-up follow

Wearable design usually runs backwards from the board's point of view. The enclosure is fixed, then the circuit is asked to fit. So the first things in the RFQ are not layer counts:

1. Outline and available volume. Rarely rectangular - expect irregular shapes, openings, keep-out zones.
2. Target finished thickness and its ceiling. This is the hardest wearable constraint. Note that finished thickness is an *outcome* of layers, dielectric thicknesses, copper weight and surface finish. It is not a parameter you can order independently.
3. Whether the design includes a bend section. This is where the most cost gets wasted.

That third point deserves its own paragraph. Wearable designs often need a circuit to wrap a curve or reach a second board, and the engineer asks whether HDI can bend. That is a category error: bend capability comes from flexible material (polyimide) and structural design, which is flex or rigid-flex territory, not an HDI build-up question. The PCB168 rigid-flex specification lists polyimide flex material, bend radius ≥1mm and 4-20 layers. So if your wearable needs to bend, what you likely need is rigid-flex, possibly carrying HDI features - not "a higher build-up HDI". Material and design detail: flex PCB applications and design guide.

Stating this in the RFQ removes a full round trip. Write "design includes a bend section, bend radius ___, expected cycles ___, please confirm a rigid-flex approach" instead of "we need very thin HDI".

In wearables, build-up level is usually forced by area and pitch: small area plus dense parts means there is not enough room to fan out, so build-up layers do the escaping. The inputs that settle it are the minimum BGA/CSP pitch and pin count, plus the area of the densest region. Given those two numbers, engineering can judge build-up level directly.

3. Tablets: lock area and density, let thickness give way

The constraint structure nearly inverts. Thickness still matters, but not at watch limits; the PCB168 multilayer page gives 0.4-6.0mm board thickness, and HDI builds on that family of structures. Three other things are what actually bind:

1. Panel dimensions and part count. Larger area means registration error gets amplified. The HDI page gives layer-to-layer registration of ±25µm as a capability. Holding that across a whole large panel, with more build-up layers stacked on it, is a different problem than holding it on a small board. That is why large-area HDI is often harder than a small board at the same build-up level.
2. High-speed interfaces and impedance. Display interfaces, memory and wireless modules mean impedance control is frequently the first stackup constraint. PCB168 publishes ±8% on the multilayer page and ±10% in the heavy-copper/HDI range (drawing confirmation governs), but to quote, engineering needs to know which groups, what target values, referenced to which standard.
3. Thermal and high-current regions. A tablet has a display, a battery and a charge path, so local copper planes and thermal paths affect copper distribution and stackup symmetry.

Tablet RFQ input order therefore runs: panel dimensions → densest-region pitch and layer intent → impedance groups → thermal/current regions. With those four, engineering can return "build-up level plus material" instead of a question.

4. Side by side: one word, two priority orders

Do not pick a column and copy it. Use the table to confirm which constraint structure your project has. Some projects are hybrids - a large wearable with a display, for instance - and then both "first constraint" rows apply, and the RFQ should say which one cannot move. That single sentence cuts round trips substantially.

5. What you specify, what the supplier decides

This is the most common root cause of a feasibility-review bounce: the buyer specified a process without supplying the conditions.

Yours to give - conditions and required outcomes:

• Device class and use case (wearable / tablet, indoor / on-body / outdoor)
• Outline, available volume, target finished thickness and its ceiling
• Minimum BGA/CSP pitch, pin count, location of densest region
• Impedance groups, target values, tolerance requirement, referenced standard and revision
• Bend section yes/no, with radius and expected cycles if yes
• Acceptance class (for example IPC-6012 Class 2 or Class 3) and standard revision
• Quantity and stage (prototype / low volume / production), which affects process routing

The supplier's to decide - engineering and quotation:

• The actual build-up level (1+N+1 versus 2+N+2 and so on)
• Whether microvias are stacked or staggered - a structural declaration, covered in stacked versus staggered microvia declaration
• Dielectric thicknesses and specific material grades (the FR-4 / BT / ABF choice)
• Lamination rounds and process sequence
• Fine-line etch compensation (inputs in HDI fine line etching RFQ inputs)

The line is simple: you supply what must be achieved, the supplier supplies how. Cross it by specifying 4+N+4 without giving pitch and thickness, and the quoting engineer can confirm neither that it is necessary nor that it is feasible. The only remaining move is to bounce it to review.

6. When feasibility review is the right answer anyway

The fair counterpoint: sometimes review is not process waste. For example when

• your minimum pitch and finished thickness combination sits near the datasheet boundary (say near 2mil/2mil line width, 0.075mm laser vias and a very thin total build at once);
• large panel area, high build-up level and tight impedance all appear together;
• a bend section overlaps a high-density region;
• ABF or BT material is needed, moving toward IC substrate territory.

In those cases engineering confirmation is a step worth taking even with complete inputs. The difference is this: with inputs complete, review confirms an approach; with inputs missing, review reconstructs your requirement. The second one is where schedule actually disappears. For judging where a supplier sits, see HDI manufacturing capability tiers, a buyer guide.

7. The input sheet: six lines, both device classes

Compressed into something you can paste into a quotation email (fill the brackets):

1. Device and use case: class [wearable / tablet / other], use case [___], expected volume [prototype / low volume / production, quantity ___].
2. Outline and thickness: outline [attach DXF or Gerber outline layer], volume restriction [___], target finished thickness [___], ceiling [___].
3. Density inputs: minimum BGA/CSP pitch [___], pin count [___], densest-region location and area [___], panel dimensions [___].
4. Electrical: controlled-impedance groups [___], targets and tolerance [___], referenced standard and revision [___]; high-current or thermally sensitive regions [___].
5. Structural specials: bend section [yes / no], if yes bend radius [___] and cycles [___]; existing stackup intent [yes / no, attach if yes].
6. Acceptance and change: acceptance class and standard revision [for example IPC-6012 Class ___, revision ___]; who triggers later changes and how they are confirmed [___].

Note the wording at the end of line 5: "existing stackup intent", not "stackup requirement". If you have an intent, attach it so engineering can check it. If you do not, say so and let engineering propose. A layer count stated with no explanation of where it came from is the single most misreadable thing in an HDI RFQ.

Quotation expectations differ between prototype and production stages - see HDI prototype and low-volume quote expectations. Once the six lines are filled, the next step is submitting the RFQ; the capability envelope is on manufacturing capabilities and the HDI PCB product page.

8. One sentence

Wearables and tablets both use HDI, but a wearable fixes volume first and squeezes routing in, while a tablet fixes density first and lets thickness give way - so build-up level should not be specified by you, it should be derived from what you supply: thickness ceiling and outline, minimum pitch, panel dimensions, impedance groups, bend or no bend, acceptance class. Six lines, and the quote no longer has to detour through feasibility review.

FAQ

Q1: Are tablet HDI and wearable HDI two different products?

Not two products - one process family solving two opposite constraint sets. Both sit inside the PCB168 HDI range (4-20 layers, 1+N+1 to 4+N+4 stackups, 0.075mm laser vias, 2mil/2mil minimum line width and space). What differs is which parameter gets locked first: a wearable locks outline and finished thickness, a tablet locks panel dimensions and part density. Different opening line in the RFQ, same input sheet underneath.

Q2: Should I just write "2+N+2" in the RFQ?

Only if that number has a source, and then say what the source is - a previously qualified stackup, a routing conclusion from your design house. A layer count with no provenance does not help quotation: engineering can confirm neither that it is necessary nor that it is achievable with your thickness and pitch combination. The more effective move is to give conditions - minimum pitch, pin count, densest-region area, finished thickness ceiling - and let the build-up level be derived.

Q3: My wearable has to bend. Does that mean a higher build-up HDI?

No. Bend capability comes from flexible material and structural design, which is flex or rigid-flex, a separate axis from HDI build-up. The PCB168 rigid-flex specification lists polyimide flex material, bend radius ≥1mm and 4-20 layers. If your wearable has a bend section, state it as "bend section present, radius ___, cycles ___" and let engineering judge whether a rigid-flex construction is required, rather than describing the need as thinner, higher build-up HDI.

Q4: Why is the same build-up level harder on a larger panel?

Because registration error is harder to hold across a large area. The ±25µm layer-to-layer figure is a capability; holding it over an entire large panel, with more build-up layers stacked on it, demands more of dimensional-change control and exposure compensation. Fine-line width consistency between panel center and edge is the same class of problem. That is why tablet-class projects must state panel dimensions - it affects feasibility as much as build-up level does.

Q5: Who declares the acceptance class?

The buyer. IPC-6012 Class 2 versus Class 3 reflects your application's reliability requirement, and a supplier should not default it for you. Declare the standard revision with it, because criteria change between revisions. IPC-6012, IPC-A-600, IPC-2226 and IPC-2315 as referenced here are industry specifications, not PCB168 internal control values; the revision cited on the drawing governs.

Q6: If my inputs are complete, can I still get sent to feasibility review?

Possibly, and legitimately: when minimum line width, minimum laser via and a very thin total build are all pushed at once, when large panel area combines with high build-up level and tight impedance, when a bend section overlaps a high-density region, or when ABF/BT material near IC substrate territory is required. With complete inputs, review confirms the approach. With missing inputs, review reconstructs your requirement - that is the version that costs schedule.