Heavy Copper PCB for Power Supply: Defining the High-Current Connection Interface in Your RFQ | PCB168
"4oz copper, 100A" is not a quotable interface specification
Most high-current RFQs we receive have the copper weight settled and the interface missing. The BOM says a terminal block, the drawing shows a pad, and nobody has written down how current is supposed to physically enter and leave the board.
That gap is not a detail deferred to production. It is the reason the quotation gets revised. Copper weight tells the fabricator how much metal to build; the interface tells them what geometry, what finish, what mask condition and what acceptance document govern the places where that metal meets something else. Two boards with identical 4oz copper and identical current can be entirely different quotations once one of them carries a bolted busbar lug and the other relies on a soldered device pad and a via array.
There is also an ownership question hiding in the same gap. A terminal, a busbar, a press-fit pin and a fastener are usually not supplied by the PCB fabricator. If the RFQ does not say who supplies each item, the quotation silently assumes one answer and the incoming inspection assumes another.
So the useful question is not "is 4oz enough". It is: at every point where current crosses from the board to something that is not the board, what has been declared, and which document decides whether it passed?
This article keeps to that question. Deriving copper weight from current and temperature rise is a separate decision and is covered in heavy copper current and thermal budget; how finished copper is expressed and measured is covered in finished copper thickness versus base copper. Neither is repeated here.
What PCB168 publishes as the boundary you are specifying inside
Interface declarations only mean something against a stated process window. The two published sources are:
From the heavy copper PCB product page: copper weight 3oz to 20oz, 1 to 16 layers, board thickness 0.8mm to 6.0mm, minimum line width 6mil, surface finish HASL, ENIG or OSP, material FR-4 TG170 or TG180, impedance control +/-10%.
From the capabilities page: 1 to 40 layers, minimum line width and spacing 2mil/2mil, minimum drill 0.1mm mechanical and 0.075mm laser, board thickness 0.2mm to 6.0mm, maximum board size 600mm x 1100mm, copper weight 0.5oz to 20oz, impedance control +/-5% TDR verified, and a quality set of per-layer AOI, 100% electrical test by flying probe or fixture, TDR coupon verification, cross-section analysis, X-ray inspection and ionic contamination testing.
Read those as two separate windows, not one merged table. The 6mil minimum line width belongs to the heavy copper route; the 2mil figure belongs to the standard capability set and does not transfer to a 20oz build. Likewise +/-10% impedance is the heavy copper page figure and +/-5% is the capabilities page figure. Any value not on those pages — current rating, temperature rise, torque, retention force — is not available for you to cite and should be treated as an engineering review item.
The four interfaces, and the four columns each one needs
Almost every high-current board resolves into some combination of four interface types. Build them as a table in your RFQ with the same four columns each time: geometry, material and finish, who supplies the hardware, which document decides acceptance.
Interface 1: bolted terminals and busbar contact faces
This is a mechanical contact area that has to conduct. What the quotation needs is the contact footprint on the board (its location, extent and the drawing view that dimensions it), the hole or slot pattern that receives the fastener, the copper condition in that area, whether that copper is bare or finished, and the flatness or local height requirement if the mating part is rigid.
Declare the fastener and lug as customer-supplied or request them as a quoted item. Do not leave it implied. Also state whether the contact face is allowed to carry identification marks or mask encroachment, because a mark placed by default inside a contact area becomes a rework argument.
What you must not do is specify the interface by its electrical duty alone. "Must carry 120A continuous" is a requirement on your design, not an instruction the fabricator can build or measure. The measurable version is geometry plus finish plus the document that judges them.
Interface 2: press-fit and mechanically loaded holes
A hole that receives a press-fit pin or a load-bearing fastener is a different animal from a plated via. For each hole family, state the terminology you are using (finished hole size or drill size — pick one and say which), the plating requirement and where it comes from, which layers the hole connects, whether the hole has a current-carrying or thermal function, and whether it is mechanically loaded.
Mechanical loading matters because it changes what is acceptable in the barrel and in the surrounding copper. If you have a retention requirement, it belongs to the hardware specification and the assembly process, not to a blanket statement on the fabrication drawing. State the controlling specification by name and let engineering review confirm what is achievable in the copper weight you have chosen.
Interface 3: parallel via arrays
A via array carrying current or heat is a designed structure, and the design side owns it. Declare the via count, the array location and pitch, the layers connected, the plating or fill requirement, and the surrounding copper and mask condition. Then state that the array is functional, not cosmetic, so it is not subject to substitution during DFM.
This is the single most common omission we see. An array drawn in the layout with no note attached looks like decoration. The fabricator can flag risk, but the fabricator cannot decide how many vias your thermal path needs. If the count is a functional minimum, write that it is a functional minimum.
Interface 4: soldered power-device pads
Here the interface is shared with assembly, which means two documents have to agree. Declare the pad geometry and its source (library reference or drawing), the mask condition around it, the finish, and the thermal relief or connection scheme to the surrounding plane. Where a pad connects to a large copper area, say explicitly whether thermal relief is permitted, because an automatically generated relief can undo the current path you designed.
If the board is being quoted as an assembly, the PCB assembly page states the input set: BOM plus fabrication data plus placement data, with assembly scope, component supply, inspection plan and test requirements confirmed in engineering review and written quotation. Power-device pads sit exactly on that boundary, so they belong in both the fabrication drawing and the assembly notes, with matching revisions.
Surface finish at the interface is a functional choice
The published finish options for heavy copper are HASL, ENIG and OSP. The decision is not a general preference — it is interface-specific. A bolted contact face, a press-fit barrel and a soldered pad do not necessarily want the same finish, and a board can legitimately need more than one.
If you need selective finish, the drawing has to show the regions. A note saying "ENIG on contact areas" without a marked region is not manufacturable as written; someone will have to guess, and the guess will be discovered at incoming inspection. Mark the area, name the finish, and state which drawing view is authoritative.
Where finish trade-offs matter to your mating hardware, the comparison in PCB surface finish comparison covers the general characteristics. Confirm availability for your specific stackup and copper weight in engineering review rather than assuming any combination is standard.
Mask openings and bare copper are requirements, not appearance
At an interface, a solder mask opening is functional. It defines where metal is exposed to make contact or accept solder. Treat it accordingly: give the opening a location, an extent, and a stated source for its dimensions, and say whether the exposed copper is to be finished or left bare.
Two specific things to write down. First, whether mask is allowed to encroach on the opening at all, and if a tolerance applies, which document sets it. Second, whether legend or identification marks are excluded from the area. Both are cheap to state up front and expensive to argue about after delivery.
Large copper areas, step changes and local geometry can all affect mask coverage. Expose those regions during DFM review, not after the purchase order.
The 6mil minimum line width constrains what sits near the interface
On the heavy copper route the published minimum line width is 6mil. That number does more than limit your power traces; it limits the control and sense signals you were planning to route past the interface.
If a current-sense pair, a gate drive or a temperature-sense line has to run near a bolted terminal or a via array, check it against 6mil before you assume the layout is buildable as one board. When a design genuinely needs finer geometry alongheavy copper, that is a mixed-requirement board and it needs engineering review before quotation — it is not a detail the fabricator can absorb.
Layer count interacts with this too. The heavy copper page publishes 1 to 16 layers, and copper weight consumes board thickness inside the 0.8mm to 6.0mm window. The interaction between those limits is worked through in thick copper multilayer layer count limits; if your interface plan assumes a layer count near the top of the range, read that first.
The five lines that belong in your RFQ
Add these to the RFQ text itself, not to an email thread:
- An interface schedule. One row per interface, with the four columns above. Reference the drawing view that dimensions each one.
- A supply split. For every terminal, lug, press-fit pin and fastener: customer-supplied, or requested as a quoted item.
- A finish map. Which finish applies where, with marked regions for any selective finish.
- A functional-structure note. Which via arrays, pad geometries and openings are functional minimums and therefore not open to substitution during DFM.
- An acceptance pointer. For each interface row, the document that decides pass or fail — fabrication drawing, controlled specification, or an agreed inspection record. Name the standard by reference where you use one.
Send that alongside the file set through the quote request, and state quantity, destination and the acceptance records you need. Lead time, minimum order quantity, equipment availability and traceability deliverables are confirmed in the written quotation, not assumed from a capability page.
When it has to go to feasibility review first
Some interface plans cannot be priced from a file set alone. Send them to engineering review before you expect a number:
- Copper weight near the top of the 3oz to 20oz range combined with a layer count near 16 and a board thickness near the 6.0mm ceiling.
- Fine control geometry required next to heavy copper, below the published 6mil minimum line width.
- Selective finish across multiple regions on the same board.
- Via arrays with a functional minimum count in an area that also has mechanical loading.
- Any interface where your mating hardware imposes a flatness, height or cleanliness requirement measured at a specific location.
Requesting review is not a delay. It is the difference between one quotation and three. You can raise it through engineering contact with the interface schedule attached.
Related links
- Heavy copper current and thermal budget
- Heavy copper PCB purchase specification and acceptance
- Thick copper multilayer layer count limits
- Heavy copper supplier process evidence request
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FAQ
Do I need to state current per interface if I already gave total board current?
Yes. Total board current does not tell anyone how that current is divided across terminals, via arrays and pads. Declare the intended function of each interface. What it cannot do is substitute for geometry — the fabricator builds geometry, not amperes.
Who supplies the terminals and lugs?
Whoever the RFQ says. There is no default. State customer-supplied or request a quoted item for each hardware item, and say whether installation is in scope. If the board is quoted as an assembly, the assembly scope is confirmed in engineering review.
Can I specify the same surface finish everywhere and sort out the interfaces later?
You can, but later is after quotation, which means a revision. If different interfaces need different finishes, mark the regions now. The published options for heavy copper are HASL, ENIG and OSP; confirm any selective combination in engineering review.
Is a via array something the fabricator can optimise?
Not if it is functional. The fabricator can identify DFM risk, but the count, location, layer connections and plating requirement of a current-carrying or thermal array are design decisions. Write the note that says so.
Why does the 6mil minimum line width apply to my signal traces?
Because it is a process window for the heavy copper route, not a rule about power traces specifically. If signals near the interface need to go finer than 6mil, that is a mixed-requirement design and needs review before quotation.
What makes an interface declaration acceptable at incoming inspection?
A location, a measurable extent, and a named document that decides pass or fail. Declarations without a controlling document get judged twice — once by the supplier and once by you — and that is where delivery disputes come from. The execution side of this is covered in incoming inspection acceptance plan.
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